Method for enhancing the memory bandwidth available through a memory module

• US 8,019,919 B2
• Filed: 09/05/2007
• Issued: 09/13/2011
• Est. Priority Date: 09/05/2007
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gower, Kevin C., Maule, Warren E.
• Primary Examiner(s): Hafiz; Tariq
• Assistant Examiner(s): YU, HENRY W
• Application Number:
  US11/850,190
• Publication Number:
  US 20110004709A1
• Time in Patent Office: 1,469 Days
• Field of Search: None
• US Class Current: 710/51
• CPC Class Codes: G06F 13/1684 using multiple buses

Abstract

A method for enhancing the memory bandwidth available through a memory module of a memory system is provided. The memory system includes a memory hub device integrated in a memory module. The memory system includes a first memory device data interface integrated in the memory hub device that communicates with a first set of memory devices integrated in the memory module. The memory system also includes a second memory device data interface integrated in the memory hub device that communicates with a second set of memory devices integrated in the memory module. In the memory system, the first set of memory devices are separate from the second set of memory devices. In the memory system, the first and second set of memory devices are communicated with by the memory hub device via the separate first and second memory device data interfaces.

Claims

1. A method of accessing memory devices of a memory module, comprising:

receiving, by a link interface of a memory hub device integrated in the memory module, a plurality of access requests for accessing a portion of one of a first set of memory devices or a second set of memory devices integrated in the memory module;

sending, by the link interface, the plurality of access requests to a memory hub controller integrated into the memory hub device;

selecting, by the memory hub controller, one or both of a first memory device data interface integrated in the memory hub device or a second memory device data interface integrated in the memory hub device, for performance of the plurality of access requests; and

responsively driving, by the memory hub controller, the first set of memory devices and the second set of memory devices using a memory device address and control bus and directing two of a read data flow selector, a first write data flow selector, or a second write data flow selector at the same time in response to receiving a plurality of access request packets from one of an external memory controller or a downstream memory hub device of another memory module, wherein, responsive to receiving a read data access request and a write data access request, the memory hub controller drives the read data flow selector to a first multiplexer of the memory hub device to select outputting read data directly from one or more of the first memory device data interface, the second memory device data interface, or a read data queue, and drives either the first write data flow selector to a second multiplexer or the second write data flow selector to a third multiplexer for selecting either a direct input from the link interface of the memory hub device or an input from a write data queue of the memory hub device, and wherein the second multiplexer provides an output to the first memory device data interface and the third multiplexer provides an output to the second memory device data interface;

accessing one of the first set of memory devices or the second set of memory devices in the memory module based on the selected first memory device data interface or the second memory device data interface, wherein;

the first memory device data interface communicates with the first set of memory devices,

the second memory device data interface communicates with the second set of memory devices,

the first set of memory devices are separate from the second set of memory devices, and

the first memory device data interface is separate from the second memory device data interface.

2. The method of claim 1, wherein the plurality of access requests are received from the external memory controller of a data processing device via a memory channel, the external memory controller being external to the memory module.

3. The method of claim 1, wherein selecting one of the first memory device data interface or the second memory device data interface comprises performing the selection in the memory hub controller integrated in the memory module, and wherein based upon the selection, the memory hub controller sends a control signal to a respective multiplexer to select either an input or output associated with one of the first memory device data interface or the second memory device data interface.

4. The method of claim 1, wherein the first set of memory devices and the second set of memory devices send and receive data to and from the external memory controller via the link interface.

5. The method of claim 1, wherein accessing one or both of the first set of memory devices or the second set of memory devices in the memory module based on the selected first memory device data interface or the second memory device data interface comprises:

processing a first memory access request via the first memory device data interface; and

processing, in parallel, a second memory access request via the second memory device data interface at a same time as the processing of the first memory access request.

6. The method of claim 1, wherein the memory module is part of a data processing device.

7. The method of claim 1, wherein the memory module is part of a main memory, of a data processing device.

8. The method of claim 1, wherein the memory module is a dual in-line memory module (DIMM).

9. The method of claim 1, wherein the memory module is a single in-line memory module (SIMM).

10. A method of accessing memory devices of a memory module, comprising:

receiving, by a link interface of a memory hub device integrated in the memory module, a plurality of access requests for accessing a portion of one of a first set of memory devices or a second set of memory devices integrated in the memory module;

sending, by the link interface, the plurality of access requests to a memory hub controller integrated into the memory hub device;

selecting, by the memory hub controller, one or both of a first memory device data interface integrated in the memory hub device or a second memory device data interface integrated in the memory hub device, for performance of the plurality of access requests; and

responsively driving, by the memory hub controller, the first set of memory devices and the second set of memory devices using a memory device address and control bus and directing two of a read data flow selector, a first write data flow selector, or a second write data flow selector at the same time in response to receiving a plurality of access request packets from one of an external memory controller or a downstream memory hub device of another memory module, wherein, responsive to receiving two write data access requests, the memory hub controller drives the first write data flow selector to a first multiplexer and the second write data flow selector to a second multiplexer for selecting either a direct input from a link interface of the memory hub device or an input from a write data queue of the memory hub device, and wherein the first multiplexer provides an output to the first memory device data interface and the second multiplexer provides an output to the second memory device data interface;

accessing one of the first set of memory devices or the second set of memory devices in the memory module based on the selected first memory device data interface or the second memory device data interface, wherein;

the first memory device data interface communicates with the first set of memory devices,

the second memory device data interface communicates with the second set of memory devices,

the first set of memory devices are separate from the second set of memory devices, and

the first memory device data interface is separate from the second memory device data interface.

11. The method of claim 10, wherein the plurality of access requests are received from the external memory controller of a data processing device via a memory channel, the external memory controller being external to the memory module.

12. The method of claim 10, wherein selecting one of the first memory device data interface or the second memory device data interface comprises performing the selection in the memory hub controller integrated in the memory module, and wherein based upon the selection, the memory hub controller sends a control signal to a respective multiplexer to select either an input or output associated with one of the first memory device data interface or the second memory device data interface.

13. The method of claim 10, wherein the first set of memory devices and the second set of memory devices send and receive data to and from the external memory controller via the link interface.

14. The method of claim 10, wherein accessing one or both of the first set of memory devices or the second set of memory devices in the memory module based on the selected first memory device data interface or the second memory device data interface comprises:

processing a first memory access request via the first memory device data interface; and

processing, in parallel, a second memory access request via the second memory device data interface at a same time as the processing of the first memory access request.

15. The method of claim 10, wherein the memory module is part of a data processing device.

16. The method of claim 10, wherein the memory module is part of a main memory of a data processing device.

17. The method of claim 10, wherein the memory module is a dual in-line memory module (DIMM).

18. The method of claim 10, wherein the memory module is a single in-line memory module (SIMM).