High endurance non-volatile memory devices
First Claim
1. A non-volatile memory device (NVMD) comprising:
- a central processing unit (CPU);
a data cache subsystem coupled to the CPU, said data cache subsystem being initialized by a method comprises;
(a) receiving a power on or reset signal in the NVMD;
(b) retrieving a tag, an index, a set number and a number-of-hits flag from a spare area of a first page of a block in the first type of NVM;
(c) loading stored data from data area of all of the pages of the block of the first type of NVM into a particular cache line in the data cache subsystem when the particular cache line is empty, wherein the particular cache line is determined by the retrieved index and the retrieved set number;
(d) otherwise loading the stored data from data area of all of the pages of the block of the first type of NVM into the particular cache line only if the retrieved number-of-hits flag shows a number greater than number-of-hits already stored in the cache line; and
repeating (a)-(d) for another block of the first type of NVM until there is no more blocks;
at least one non-volatile memory (NVM) module configured as a data storage of a host as the NVMD is operatively adapted to the host, said at least one non-volatile memory module having first and second types of NVM arranged in a hierarchical scheme with the first type of NVM configured as a buffer between the data cache subsystem and the second type of NVM;
a NVM controller, coupling to the CPU, configured for managing said at least one NVM module; and
an input/output (I/O) interface, coupling to the NVM controller, configured for receiving incoming data from the host to the data cache subsystem and configured for sending outgoing data from the data cache subsystem to the host.
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Accused Products
Abstract
High endurance non-volatile memory devices (NVMD) are described. A high endurance NVMD includes an I/O interface, a NVM controller, a CPU along with a volatile memory subsystem and at least one non-volatile memory (NVM) module. The volatile memory cache subsystem is configured as a data cache subsystem. The at least one NVM module is configured as a data storage when the NVMD is adapted to a host computer system. The I/O interface is configured to receive incoming data from the host to the data cache subsystem and to send request data from the data cache subsystem to the host. The at least one NVM module may comprise at least first and second types of NVM. The first type comprises SLC flash memory while the second type MLC flash. The first type of NVM is configured as a buffer between the data cache subsystem and the second type of NVM.
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Citations
18 Claims
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1. A non-volatile memory device (NVMD) comprising:
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a central processing unit (CPU); a data cache subsystem coupled to the CPU, said data cache subsystem being initialized by a method comprises; (a) receiving a power on or reset signal in the NVMD; (b) retrieving a tag, an index, a set number and a number-of-hits flag from a spare area of a first page of a block in the first type of NVM; (c) loading stored data from data area of all of the pages of the block of the first type of NVM into a particular cache line in the data cache subsystem when the particular cache line is empty, wherein the particular cache line is determined by the retrieved index and the retrieved set number; (d) otherwise loading the stored data from data area of all of the pages of the block of the first type of NVM into the particular cache line only if the retrieved number-of-hits flag shows a number greater than number-of-hits already stored in the cache line; and repeating (a)-(d) for another block of the first type of NVM until there is no more blocks; at least one non-volatile memory (NVM) module configured as a data storage of a host as the NVMD is operatively adapted to the host, said at least one non-volatile memory module having first and second types of NVM arranged in a hierarchical scheme with the first type of NVM configured as a buffer between the data cache subsystem and the second type of NVM; a NVM controller, coupling to the CPU, configured for managing said at least one NVM module; and an input/output (I/O) interface, coupling to the NVM controller, configured for receiving incoming data from the host to the data cache subsystem and configured for sending outgoing data from the data cache subsystem to the host. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A multi-processor non-volatile memory device (NVMD) comprising:
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a plurality of internal non-volatile memory devices; a first central processing unit (CPU) configured for managing and controlling the plurality of internal non-volatile memory devices coupled therewith, wherein each of the plurality of internal non-volatile memory devices includes; a second CPU; a data cache subsystem coupled to the second CPU, said data cache subsystem being initialized by a method comprises; (a) receiving a power on or reset signal in the NVMD; (b) retrieving a tag, an index, a set number and a number-of-hits flag from a spare area of a first page of a block in the first type of NVM; (c) loading stored data from data area of all of the pages of the block of the first type of NVM into a particular cache line in the data cache subsystem when the particular cache line is empty, wherein the particular cache line is determined by the retrieved index and the retrieved set number; (d) otherwise loading the stored data from data area of all of the pages of the block of the first type of NVM into the particular cache line only if the retrieved number-of-hits flag shows a number greater than number-of-hits already stored in the cache line; and repeating (a)-(d) for another block of the first type of NVM until there is no more blocks; and at least one non-volatile memory (NVM) module configured as a data storage of a host as the NVMD is operatively adapted to the host, said at least one non-volatile memory module having first and second types of NVM arranged in a hierarchical scheme with the first type of NVM configured as a buffer between the data cache subsystem and the second type of NVM. - View Dependent Claims (16, 17, 18)
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Specification