Memory write signaling and methods thereof

• US 8,019,958 B2
• Filed: 09/03/2010
• Issued: 09/13/2011
• Est. Priority Date: 10/10/1997
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Gasbarre, James A., Abhyankar, Abhijit M., Barth, Richard M., Nguyen, David, Hampel, Craig E., Stark, Donald C., Ware, Frederick A., Davis, Paul G.
• Primary Examiner(s): Bataille; Pierre-Michel
• Application Number:
  US12/875,483
• Publication Number:
  US 20100332719A1
• Time in Patent Office: 375 Days
• Field of Search: 711/5, 711/167, 711/E12.001, 711/E12.084
• US Class Current: 711/167
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/2218 Late write
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

In a method of controlling a memory device, the following is conveyed over a first set of interconnect resources: a first command that specifies activation of a row of memory cells; a second command that specifies a write operation, wherein write data is written to the row; a bit that specifies whether precharging occurs after the write data is written; and a code that specifies whether data mask information will be issued for the write operation. If the code specifies that the information will be issued, then the information, which specifies whether to selectively write portions of the write data, is conveyed over the first set of interconnect resources after conveying the code. The write data to be written in connection with the write operation is conveyed over a second set of interconnect resources that is separate from the first set of interconnect resources.

Claims

1. A method of controlling a memory device, the method comprising:

over a first set of interconnect resources;

conveying a first command that specifies activation of a row of memory cells;

conveying a second command that specifies a write operation, wherein write data associated with the write operation is written to the row of memory cells;

conveying a bit that specifies whether precharging occurs after the write data is written;

conveying a code that specifies whether data mask information will be issued in connection with the write operation; and

if the code specifies that the data mask information will be issued, then conveying the data mask information after conveying the code, wherein the data mask information specifies whether to selectively write portions of the write data; and

over a second set of interconnect resources that is separate from the first set of interconnect resources, conveying the write data to be written in connection with the write operation.

2. The method of claim 1, wherein conveying the data mask information comprises conveying, over a signal line of the first set of interconnect resources, two bits of the data mask information during a clock cycle of a clock signal that is received by the memory device.

3. The method of claim 1, further comprising, over the first set of interconnect resources, conveying a column address that identifies a subset of memory cells in the row such that the write data is written to the subset of memory cells in the row.

4. The method of claim 3, further comprising:

conveying a first bank address that is associated with the first command, the first bank address to identify a bank of a plurality of memory cell banks in which to perform the activation; and

conveying a second bank address that is associated with the second command and the column address, such that the second command specifies the write operation to be performed in a bank identified by the second bank address.

5. The method of claim 4, wherein:

the first command and first bank address are conveyed over a first portion of the first set of interconnect resources, and

the second command, second bank address, column address, bit, and code are conveyed over a second portion of the first set of interconnect resources.

6. The method of claim 5, wherein:

the first command and first bank address are conveyed in a first packet over the first portion of the first set of interconnect resources, and

the second command, second bank address, column address, bit, and code are conveyed in a second packet over the second portion of the first set of interconnect resources.

7. The method of claim 6, wherein:

the first portion of the first set of interconnect resources is a primary interconnect consisting of three signal lines,

the second portion of the first set of interconnect resources is a secondary interconnect consisting of five signal lines, and

the second set of interconnect resources is a data bus consisting of eighteen signal lines.

8. A method of controlling a memory device having a plurality of banks, the method comprising:

conveying a first command and a first bank address to activate a row in a bank identified by the first bank address;

conveying a second command and a second bank address, the second command specifying a write operation of write data to a bank identified by the second bank address;

conveying a code that specifies whether data mask information will be issued in connection with the write operation;

if the code specifies that the data mask information will be conveyed, then conveying the data mask information after conveying the code, the data mask information specifying whether to selectively write portions of the write data; and

conveying the write data associated with the write operation, wherein the write data is conveyed over signal lines separate from those used to convey the first command, first bank address, second command, second bank address, and code.

9. The method of claim 8, wherein:

the first command and first bank address are conveyed in a first packet over first interconnect resources, and

the second command and code are conveyed in a second packet over second interconnect resources.

10. The method of claim 9, wherein:

the first interconnect resources are a primary interconnect consisting of three signal lines, and

the second interconnect resources are a secondary interconnect consisting of five signal lines.

11. The method of claim 8, further comprising conveying a column address that identifies a column associated with the write operation, wherein both a bit of the second bank address and a bit of the column address are conveyed over a common signal line during a clock cycle of a clock signal.

12. The method of claim 11, further comprising conveying a first bit that specifies whether precharging occurs after the write data is written, wherein the code and first bit are conveyed synchronously with respect to a first transition of the clock signal.

13. The method of claim 12, wherein the column address and the data mask information are conveyed synchronously with respect to transitions of the clock signal which succeed the first transition of the clock signal.

14. The method of claim 8, wherein conveying the data mask information comprises conveying, on a signal line, two bits of the data mask information during a clock cycle of the clock signal.

15. The method of claim 8, further comprising conveying a column address that identifies a column associated with the write operation, wherein the first bank address and the second bank address identify the same bank of the plurality of banks, such that the column address identifies a column of the row activated in the same bank identified by both the first and second bank address.

16. The method of claim 8, wherein the first bank address identifies a first bank of the plurality of banks and the second bank address identifies a second bank of the plurality of banks, wherein the first bank and second bank are different banks.

17. The method of claim 8, wherein:

the first command and first bank address are conveyed over first interconnect resources, and

the second command, second bank address, and code are conveyed over second interconnect resources,

wherein the first interconnect resources are separate from the second interconnect resources.

18. A method of operation of a memory controller that controls a memory device, the method comprising:

conveying a first command that specifies activation of a row of memory cells;

conveying a second command that specifies a write operation to the memory device, wherein write data is to be written to the row in connection with the write operation;

conveying, via a first signaling resource, a code that specifies whether data mask information will be issued in connection with the write operation, wherein the code is conveyed synchronously with respect to a first transition of a clock signal;

conveying the write data over a set of signal lines that are separate from signal lines used to convey the first command and the second command; and

if the code specifies that the data mask information will be issued, then conveying two bits of the data mask information over the first signaling resource during a clock cycle of the clock signal, the data mask information to specify whether to selectively write portions of the write data to the memory core.

19. The method of claim 18, further comprising conveying, on a second signaling resource, precharge information that specifies whether precharging occurs after the write data is written, wherein the precharge information is conveyed synchronously with respect to the first transition of the clock signal.

20. The method of claim 18, further comprising conveying column address information associated with the write operation, wherein the column address information identifies a subset of memory cells in the row such that the write data is written to the subset of memory cells in the row in connection with the write operation.

21. The method of claim 20, further comprising conveying, on a second signaling resource, precharge information that specifies whether precharging occurs after the write data is written, wherein:

the precharge information is conveyed synchronously with respect to the first transition of the clock signal, and

a portion of the column address information is conveyed, over the first signaling resource and the second signaling resource, synchronously with respect to a transition of the clock signal that succeeds the first transition of the clock signal.

22. The method of claim 18, wherein:

the signal lines used to convey the first command and the second command comprise a primary interconnect and a secondary interconnect;

the first command is conveyed over the primary interconnect, which is separate from the first signaling resource, and

the second command is conveyed over the secondary interconnect, which is separate from the primary interconnect.

23. The method of claim 22, wherein:

the first command, conveyed over the primary interconnect, is included in a first packet format; and

the second command, conveyed over the secondary interconnect, is included in a second packet format.

24. The method of claim 22, wherein:

the primary interconnect consists of three signal lines, and

the secondary interconnect consists of five signal lines.