Nonvolatile memory system

• US 8,019,959 B2
• Filed: 02/04/2008
• Issued: 09/13/2011
• Est. Priority Date: 02/09/2007
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Nguyen, Lau, Lee, Chi-Kong, Sutardja, Pantas, Wu, Zining, Yoon, Tony
• Primary Examiner(s): Ellis; Kevin L
• Assistant Examiner(s): Bertram; Ryan
• Application Number:
  US12/025,371
• Publication Number:
  US 20080195810A1
• Time in Patent Office: 1,317 Days
• Field of Search: 711/103, 711/154, 711170-171
• US Class Current: 711/171
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0661 Format or protocol conversion arrangements
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

A nonvolatile (NV) memory system includes a memory control module that encodes data to provide encoded logical data structures. The system also includes NV memory that includes X arrays that include physical data structures that differ in size from the encoded logical data structures. The memory control module writes/reads from the NV memory according to the encoded logical data structures. X is an integer greater than or equal to 1.

Claims

1. A nonvolatile memory system, comprising:

a memory control module configured to encode data to provide encoded logical data structures; and

a nonvolatile memory comprising X arrays, wherein the X arrays include physical data structures, wherein each of the X arrays are implemented on a respective chip, wherein a size of the physical data structures is different than a size of the encoded logical data structures, and wherein X is an integer greater than or equal to 1,

wherein the memory control module is configured to write to and read from the nonvolatile memory according to the size of the encoded logical data structures,

wherein the memory control module is configured to allocate (i) a first portion of a first physical page of the nonvolatile memory for storing a first portion of a first one of the encoded logical data structures and (ii) a second portion of the first physical page for storing a first portion of a second one of the encoded logical data structures,

wherein the memory control module is configured to store (i) a first portion of a third one of the encoded logical data structures in a first row of a X^th one of the X arrays and (ii) a second portion of the third one of the encoded logical data structures in a second row of a first one of the X arrays.

2. The system of claim 1, wherein the memory control module is configured to send and receive the data in logical data structures.

3. The system of claim 2, wherein the logical data structures comprise at least one of logical pages or logical blocks.

4. The system of claim 1, wherein the physical data structures comprise at least one of physical pages or physical blocks in the nonvolatile memory.

5. The system of claim 1, wherein:

the memory control module comprises an encoder module; and

the encoder module is configured to select one of N error correction code rates, wherein N is an integer greater than 1.

6. The system of claim 5, wherein the encoder module is configured to perform encoding according to at least one of (i) a Reed Solomon scheme, (ii) a Bose-Chaudhuri-Hocquenghem scheme, (iii) a Low Density Parity Check scheme, (iv) a Gray code scheme, or (v) a combination of two or more of the Bose-Chaudhuri-Hocquenghem scheme, the Low Density Parity Check scheme, and the Gray code scheme.

7. The system of claim 5, wherein the memory control module further comprises a decoder module configured to decode the encoded logical data structures during a read operation from the nonvolatile memory.

8. The system of claim 1, wherein the memory control module is configured to write to the X arrays in parallel when X is greater than 1.

9. The system of claim 8, wherein the memory control module is configured to write the first portion of the first one of the encoded logical data structures to a first one of the X arrays while writing a second portion of the first one of the encoded logical data structures to a second one of the X arrays.

10. The system of claim 9, wherein the memory control module is configured to write the first portion of the second one of the encoded logical data structures to the second one of the X arrays while writing (i) the first portion of the first of the encoded logical data structures and (ii) the second portion of the first of the encoded logical data structures.

11. The system of claim 8, wherein the memory control module is configured to:

allocate buffers within the X arrays for each of the encoded logical data structures; and

store portions of the encoded logical data structures that do not fit into the physical data structures in the buffers.

12. The system of claim 8, further comprising a plurality of memory chips, wherein each of the X arrays corresponds to a respective one or more of the plurality of memory chips.

13. The system of claim 1, wherein the memory control module is configured to determine an amount of data to erase in the nonvolatile memory based on the size of the encoded logical data structures.

14. The system of claim 13, wherein the amount of data includes data within a predetermined number of cells within all of the X arrays.

15. The system of claim 2, further comprising a memory drive comprising the memory control module and the nonvolatile memory.

16. The system of claim 15, further comprising a host device in communication with the memory drive according to the logical data structures.

17. The system of claim 1, wherein the nonvolatile memory comprises at least one of flash memory, static random access memory, nitride read only memory, phase change memory, magnetic random access memory or multi-state memory.

18. The system of claim 1, wherein the size of the physical data structures and the size of the encoded logical data structures do not have an integer relationship.

19. The system of claim 1, wherein:

each of the X arrays comprises a plurality of erase blocks;

each of the plurality of erase blocks comprises a plurality of pages including the first physical page; and

the memory control module allocates (i) a first portion of one of the plurality of erase blocks for storing the first one of the encoded logical data structures (ii) a second portion of the one of the plurality of erase blocks for storing the first portion of the second one of the encoded logical data structures.

20. The system of claim 19, wherein the memory control module is configured to simultaneously erase data stored in all cells of one of the plurality of erase blocks.

21. The system of claim 19, wherein:

a first one of the X arrays comprises the first erase block; and

a second one of the X arrays comprises the second erase block.

22. The system of claim 1, wherein:

when a size of a coded logical block of data matches a size of a physical block of the nonvolatile memory, the memory control module accesses the nonvolatile memory according to the size of the physical block; and

when the size of the coded logical block of data does not match the size of the physical block, the memory control module accesses the nonvolatile memory according to at least one of (i) the size of the coded logical block of data or (ii) a size of a logical page of data.

23. The system of claim 1, wherein:

the first one of the encoded logical data structures is a first logical page of data; and

the second one of the encoded logical data structures is a second logical page of data.

24. The system of claim 1, wherein the memory control module allocates:

the first portion of the first physical page for storing the first one of the encoded logical data structures;

the second portion of the first physical page for storing the first portion of the second one of the encoded logical data structures; and

a second physical page for storing a second portion of the second one of the encoded logical data structures.

25. The system of claim 1, wherein:

the memory control module is configured to encode the data to generate the encoded logical data structures based on the selected one of N error correction code rates; and

each of the encoded logical data structures is larger in size than the size of the physical data structures.

26. The system of claim 25, wherein a size of the second portion of the third one of the encoded logical data structures is based on the selected one of the N error correction code rates.

43. The system of claim 1, wherein the memory control module allocates (i) a first buffer of the first physical page for storing the first portion of the first one of the encoded logical data structures and (ii) a second buffer of the first physical page for storing the first portion of the second one of the encoded logical data structures.

27. A method for operating a nonvolatile memory system, the method comprising:

encoding data to provide encoded logical data structures;

writing to and reading from a nonvolatile memory according to a size of the encoded logical data structures, wherein the nonvolatile memory comprises X arrays, wherein each of the X arrays are implemented on a respective chip, wherein the X arrays include physical data structures, wherein a size of the physical data structures is different than the size of the encoded logical data structures, and wherein X is an integer greater than or equal to 1;

allocating (i) a first portion of a first physical page of the nonvolatile memory for storing a first portion of a first one of the encoded logical data structures and (ii) a second portion of the first physical page for storing a first portion of a second one of the encoded logical data structures; and

storing (i) the first portion of a third one of the encoded logical data structures in a first row of a Xth one of the X arrays and (ii) a second portion of a third one of the encoded logical data structures in a second row of a first one of arrays.

28. The method of claim 27, further comprising sending and receiving the data in logical data structures.

29. The method of claim 28, wherein the logical data structures comprise at least one of logical pages or logical blocks.

30. The method of claim 27, wherein the physical data structures comprise at least one of physical pages or physical blocks in the nonvolatile memory.

31. The method of claim 27, further comprising selecting one of N error correction code rates, wherein N is an integer greater than 1.

32. The method of claim 31, further comprising encoding the data according to at least one of (i) a Reed Solomon scheme, (ii) a Bose-Chaudhuri-Hocquenghem scheme, (iii) a Low Density Parity Check Low Density Parity Check scheme, (iv) a Gray code scheme, or (v) a combination of two or more of the Bose-Chaudhuri-Hocquenghem scheme, the Low Density Parity Check scheme, and the Gray code scheme.

33. The method of claim 31, further comprising decoding the encoded logical data structures during a read operation from the nonvolatile memory.

34. The method of claim 27, further comprising writing to the X arrays in parallel when X is greater than 1.

35. The method of claim 34, further comprising writing the first portion of the first one of the encoded logical data structures to a first one of the X arrays while writing a second portion of the first one of the encoded logical data structures to a second one of the X arrays.

36. The method of claim 35, further comprising writing the first portion of the second one of the encoded logical data structures to the second one of the X arrays while writing (i) the first portion of the first one of the encoded logical data structures and (ii) the second portion of the first one of the encoded logical data structures.

37. The method of claim 34, further comprising:

allocating buffers within the X arrays for each of the encoded logical data structures; and

storing portions of the encoded logical data structures that do not fit into the physical data structures in the buffers.

38. The method of claim 34, wherein each of the X arrays corresponds to a respective one or more memory chips.

39. The method of claim 27, further comprising determining an amount of data to erase in the nonvolatile memory based on the size of the encoded logical data structures.

40. The method of claim 39, wherein the amount of data includes data within a predetermined number of cells within all of the X arrays.

41. The method of claim 27, wherein the nonvolatile memory comprises at least one of flash memory, static random access memory, nitride read only memory, phase change memory, magnetic random access memory or multi-state memory.

42. The method of claim 27, wherein the size of the physical data structures and the size of the encoded logical data structures do not have an integer relationship.