Pipeline processor with write control and validity flags for controlling write-back of execution result data stored in pipeline buffer register

• US 8,019,974 B2
• Filed: 01/12/2009
• Issued: 09/13/2011
• Est. Priority Date: 01/17/2008
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tanabe, Jun
• Primary Examiner(s): Kim; Kenneth S
• Application Number:
  US12/352,154
• Publication Number:
  US 20090187749A1
• Time in Patent Office: 974 Days
• Field of Search: None
• US Class Current: 712/218
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/3867 using instruction pipelines

Abstract

A bypass circuit is provided in a pipeline processor. A pipeline register is provided between an instruction execution stage and a write-back stage. The pipeline register stores a data validity flag and a WRITE control flag to control writing data into a general purpose register unit. The data retained in the pipeline register is allowed to be written back into the general purpose register unit when the WRITE control flag indicates “valid”. The pipeline register continues to retain the retained data even after the writing of the retained data into the general purpose register unit. The first pipeline register supplies the retained data to the second stage through the bypass circuit at the time of executing a subsequent instruction having data dependency on a preceding instruction.

Claims

1. A pipeline processor including a first stage to read data from a general purpose register unit, a second stage to execute instruction, and a third stage to write back data into the general purpose register unit, the pipeline processor comprising:

a first pipeline register to retain data obtained by the execution in the second stage and to allow the data to be written back into the general purpose register unit, the first pipeline register being provided between the second stage and the third stage, the first pipeline register including a first area to store a data validity flag indicating validity of the retained data and a second area to store a WRITE control flag to control writing the retained data into the general purpose register unit, and, the data retained in the first pipeline register being allowed to be written back into the general purpose register unit when the WRITE control flag indicates “

valid”

; and

a bypass circuit to supply the data retained in the first pipeline register to the second stage when the data validity flag indicates “

valid,”

wherein

the data validity flag and the WRITE control flag become “

valid”

when each of preceding and subsequent instructions for rewriting the general purpose register reaches the third stage,

the WRITE control flag becomes “

invalid”

when the data retained in the first pipeline register is written into the general purpose register unit, and

the data validity flag becomes “

invalid”

when a subsequent instruction is provided to the third stage that invalidates the data retained in the first pipeline register, and wherein

the first pipeline register continues to retain the retained data even after the writing of the retained data into the general purpose register unit, and

the first pipeline register provides the retained data to the second stage through the bypass circuit at the time of executing a subsequent instruction having data dependency on a preceding instruction.

2. A pipeline processor including a first stage to read data from a general purpose register unit, a second stage to execute instruction, and a third stage to write back the data into the general purpose register unit, the pipeline processor comprising:

a first pipeline register provided between the second stage and the third stage, the first pipeline register including a first area to store a data validity flag indicating validity of data retained by the first pipeline register and a second area to store a WRITE control flag to control writing the retained data into the general purpose register unit, the data retained in the first pipeline register being allowed to be written back into the general purpose register when the WRITE control flag indicates “

valid”

;

a second pipeline register provided between the first stage and the second stage;

one of a first arithmetic logic unit and a first memory to execute instruction in the second stage, the one of the first arithmetic logic unit and the first memory being supplied with data from the second pipeline register and supplying output data to the first pipeline register;

a bypass circuit to selectively supply the data retained in the first pipeline register to the second pipeline register when the data validity flag indicates “

valid,”

wherein

the data validity flag and the WRITE control flag become “

valid”

when each of preceding and subsequent instructions for rewriting the general purpose register reaches the third stage,

the WRITE control flag becomes “

invalid”

when the data retained in the first pipeline register is written into the general purpose register unit, and

the data validity flag becomes “

invalid”

when a subsequent instruction is provided to the third stage that invalidates the data retained in the first pipeline register, and wherein

the first pipeline register continues to retain the retained data even after the writing of the retained data into the general purpose register unit ends, and

the first pipeline register provides the retained data to the second pipeline register through the bypass circuit at the time of executing a subsequent instruction having data dependency on a preceding instruction.

3. The pipeline processor according to claim 2, wherein

the bypass circuit includes a first selector, and

the first selector selectively supplies one of data retained in the general purpose register unit and the data retained in the first pipeline register, to the second pipeline register, depending on the data validity flag of the first pipeline register.

4. The pipeline processor according to claim 2, further comprising:

a third pipeline register provided between the second stage and the third stage, the third pipeline register including a third area to store a data validity flag indicating validity of data retained by the third pipeline register and a fourth area to store a WRITE control flag to control writing the retained data into the general purpose register unit, the data retained in the first pipeline register is allowed to be written back into the general purpose register unit, when the WRITE control flag indicates “

valid”

;

a fourth pipeline register provided between the first stage and the second stage;

one of a second arithmetic logic unit and a second memory which is supplied with data from the second pipeline register and supplies output data to the second pipeline register; and

a first selector to supply the data retained in the first pipeline register and the data retained in the second pipeline register, selectively to the bypass circuit and the general purpose register unit, wherein

the bypass circuit has a second selector,

the third pipeline register continues to retain the retained data even after the writing of the retained data into the general purpose register unit,

the third pipeline register supplies the retained data to the fourth pipeline register through the second selector of the bypass circuit at the time of executing a subsequent instruction having data dependency on a preceding instruction.

5. The pipeline processor according to claim 2, wherein the bypass circuit has a first selector, and the first selector selectively supplies an output of one of the first arithmetic logic unit and the first memory to the second pipeline register.

6. The pipeline processor according to claim 5, further comprising:

a third pipeline register provided between the first stage and the second stage;

one of a second arithmetic logic unit and a second memory to execute instruction in the second stage; and

a second selector, wherein

the bypass circuit includes a third selector to selectively supply an output of the second selector and an output of a fourth selector of the bypass circuit to the third pipeline register, and

the second selector selectively supplies an output of one of the first arithmetic logic unit and the first memory, and an output of one of the second arithmetic logic unit and the second memory, to the first selector and the third selector.