Layout quality gauge for integrated circuit design

• US 8,020,120 B2
• Filed: 10/01/2007
• Issued: 09/13/2011
• Est. Priority Date: 10/01/2007
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Sing, Rama Nand, Yee, Fanchieh, Ludwig, Thomas, Heng, Fook-Luen, Lavin, Mark A., Lee, Jin-Fuw
• Primary Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US11/865,252
• Publication Number:
  US 20090089726A1
• Time in Patent Office: 1,443 Days
• Field of Search: None
• US Class Current: 716/52
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A method for layout design includes steps or acts of: receiving a layout for design of an integrated circuit chip; designing mask shapes for the layout; transmitting the mask shapes to a litho simulator for generating wafer shapes; receiving the wafer shapes; calculating electrically equivalent gate lengths for the wafer shapes; analyzing the gate lengths to check for conformity against a threshold value, wherein the threshold value represents a desired value of electrically equivalent gate lengths; placing markers on the layout at those locations where the gate length violates the threshold value; and generating a histogram of gate lengths for comparing layouts for electrically equivalent gate lengths for layout quality.

Claims

1. A system for assessing and enforcing layout quality in terms of uniformity of gate lengths derived from wafer shapes in very large scale integrated chip (VLSI) design, the system comprising:

a processor configured for;

receiving as input a layout of a VLSI chip;

obtaining a description of a plurality of gates on the layout, comprising obtaining a threshold value for a predetermined uniformity of gate length; and

obtaining a description of process variability specifying process conditions;

a shape processor configured for obtaining wafer shapes to compute gates over the layout for each process point in a process window;

the processor further configured for;

describing the layout by measuring the device dependent electrically-equivalent gate lengths of said plurality of gates from their corresponding wafer shapes;

measuring the device dependent electrically-equivalent gate lengths of said plurality of gates from their corresponding wafer shapes that are equivalent with respect to device off-current;

determining any gate within said plurality of gates that violates the predetermined uniformity of gate length threshold; and

flagging the gates that violate the threshold as outliers, wherein the flagging comprises placing a marker on the layout where the outlier is located; and

a tool for generating a histogram of gate lengths across the layout and across the process window, wherein a number and magnitude of the violation serves as a layout quality gauge.

2. The system of claim 1 further comprising a computer-aided design tool used for flagging the gates.

3. The system of claim 1 wherein a Monte Carlo method is used for measuring the device dependent electrically-equivalent gate lengths.

4. The system of claim 1 wherein the tool is implemented as software.

5. The system of claim 1 wherein the tool is implemented as hardware.

6. The system of claim 1 wherein the tool is implemented as firmware.

7. The system of claim 1 further comprising:

at least one delay current table; and

at least one leakage current table.

8. The system of claim 7 further comprising device models used to calculate equivalent gate lengths using both the delay and the leakage tables.

9. The system of claim 1 further comprising:

a litho simulator.

10. A method for layout design, the method comprising steps of:

using a processor for;

receiving a layout for design of an integrated circuit chip;

obtaining a description of process variability specifying process conditions;

obtaining mask shapes designed for the layout, subject to the specified process conditions to compute gates over the layout for each process point in a process window;

transmitting the mask shapes to a litho simulator for generating wafer shapes;

receiving the wafer shapes from the litho simulator;

calculating electrically equivalent gate lengths for the wafer shapes;

analyzing the gate lengths for conformance to threshold values, wherein the threshold values represent acceptable values of electrically equivalent gate lengths;

placing markers on the layout at those locations where the gate length violates the threshold value; and

generating a histogram of the gate lengths for comparing the layout to other layouts for layout quality by checking conformity to specified variations of electrically equivalent gate lengths.

11. The method of claim 10 wherein the analyzing step comprises implementing a Monte Carlo method.

12. The method of claim 10 wherein the calculating step comprises a step of:

determining gate lengths by device models to calculate equivalent gate lengths using both delay and leakage tables.

13. The method of claim 10 wherein the step of placing markers comprises using a computer-aided design tool.

14. The method of claim 10 wherein the step of generating the histogram comprises steps of:

graphically representing a number and magnitude of outliers, wherein the outliers are the gate lengths that violate the threshold value; and

using the graphical representation as the layout quality gauge.

15. The method of claim 14 further comprising a step of:

fixing the outliers.

16. The method of claim 10 wherein at least one of the steps is performed by program code executed as software.

17. The method of claim 10 further comprising a step of:

annotating the gates on the layout using serial identification.

18. A computer program product tangibly embodied on a non-transitory computer readable medium and storing code that, when executed, causes a computer to perform a method comprising:

receive a layout for design of an integrated circuit chip;

obtaining a description of process variability specifying process conditions;

obtain mask shapes designed for the layout, subject to the specified process conditions to compute gates over the layout for each process point in a process window;

transmit the mask shapes to a litho simulator for generating wafer shapes;

receive the generated wafer shapes from the litho simulator;

calculate electrically equivalent gate lengths for the wafer shapes;

analyze the gate lengths to check conformity against a threshold value, wherein the threshold value represents a desired value of electrically equivalent gate length;

place markers on the layout at those locations where the gate length violates the threshold value; and

generate a histogram of gate lengths for comparing the layout to other layouts for layout quality by checking conformity to specified variation of electrically equivalent gate lengths.