Manufacturing aware design and design aware manufacturing of an integrated circuit

• US 8,020,135 B2
• Filed: 06/09/2008
• Issued: 09/13/2011
• Est. Priority Date: 05/20/2005
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Scheffer, Louis K., Fujimura, Akira
• Primary Examiner(s): ROSSOSHEK, YELENA
• Application Number:
  US12/136,044
• Publication Number:
  US 20080307371A1
• Time in Patent Office: 1,191 Days
• Field of Search: 716 1- 18
• US Class Current: 716/126
• CPC Class Codes: G03F 7/70125 Use of illumination settings tailored to particular mask patterns details of setting means G03F7/70091

Abstract

Some embodiments of the invention provide a process for designing and manufacturing an integrated circuit (“IC”). The process selects a wiring configuration and an illumination configuration. The process uses the selected wiring configuration to design an IC layout. The process then uses the selected illumination configuration to manufacture the IC based on the designed IC layout. Some embodiments select a wiring configuration based on the selected illumination configuration. In some embodiments, selecting the illumination configuration entails selecting at least one stepper lens for the IC layout, where the stepper lens illuminates at least one mask for at least one particular layer of the IC layout. Also, in some embodiments, selecting the wiring configuration entails defining the width and/or spacing of the routes along different directions on at least one particular wiring layer of the IC layout.

Claims

1. A manufacturing aware process for designing an integrated circuit (“

IC”

) layout, the process comprising;

specifying a stepper lens for a particular layer of the IC layout as part of an illumination configuration;

at a computing device, defining a wiring configuration based on the illumination configuration; and

using the defined wiring configuration to route the IC layout.

2. The process of claim 1, wherein defining the wiring configuration comprises defining a first width for a first route and a second width for a second route for each layer of the IC layout based on the specified stepper lens.

3. The process of claim 1, wherein specifying the stepper lens comprises specifying at least one of an octagonal lens and an annular lens for a first the particular layer of the IC layout.

4. A manufacturing aware process for designing an integrated circuit (“

IC”

) layout, the process comprising;

specifying a dipole lens for a first layer of the IC layout as part of an illumination configuration, wherein the dipole lens comprises two poles;

at a computing device, defining a wiring configuration based on the illumination configuration; and

using the defined wiring configuration to route the IC layout.

5. The process of claim 4, wherein defining the wiring configuration comprises defining a narrow route in a first direction and a wide route in a second direction different from the first direction for the first layer of the IC layout when the two poles of the dipole lens are aligned in a direction that is perpendicular to the first direction.

6. The process of claim 5, wherein the first direction is a horizontal direction when the two poles of the dipole lens are vertically aligned.

7. The process of claim 5, wherein the first direction is a vertical direction when the two poles of the dipole lens are horizontally aligned.

8. The process of claim 5, wherein the first direction is a 135°

diagonal direction when the two poles of the dipole lens are 45°

diagonally aligned.

9. The process of claim 5, wherein the first direction is a 45°

diagonal direction when the two poles of the dipole lens are 135°

diagonally aligned.

10. The process of claim 4, wherein the dipole lens is a first dipole lens, wherein the process further comprises specifying a second dipole lens for the first layer of the IC layout, the second dipole lens comprises two poles.

11. The process of claim 10, wherein defining the wiring configuration comprises defining a narrow route in a first direction, a narrow route in a second direction, and a wide route in a third direction different from the first and second directions for the first layer of the IC layout when the two poles of the first dipole lens are aligned in a direction that is perpendicular to the first direction and the two poles of the second dipole lens are aligned in a direction that is perpendicular to the second direction.

12. The process of claim 11, wherein the first direction is a horizontal direction when the two poles of the first dipole lens are vertically aligned, and the second direction is a vertical direction when the two poles of the second dipole lens are horizontally aligned.

13. The process of claim 11, wherein the first direction is a 135°

diagonal direction when the two poles of the first dipole lens are 45°

diagonally aligned, and the second direction is a 45°

diagonal direction when the two poles of the second dipole lens are 135°

diagonally aligned.

14. The process of claim 4, wherein the poles of the dipole lens comprise at least one of a circular shape, a non-circular shape, and an elliptical shape.

15. A manufacturing aware process for designing an integrated circuit (“

IC”

) layout, the process comprising;

specifying a quadrupole lens for a first layer of the IC layout as part of an illumination configuration, wherein the quadrupole lens comprises four poles;

at a computing device, defining a wiring configuration based on the illumination configuration; and

using the defined wiring configuration to route the IC layout.

16. The process of claim 15, wherein defining the wiring configuration comprises defining a narrow route in a first direction, a narrow route in a second direction, and a wide route in a third direction different from the first and second directions for the first layer of the IC layout when the first and second poles of the quadrupole lens are aligned in a direction that is perpendicular to the first direction, and the third and fourth poles of the quadrupole lens are aligned in a direction that is perpendicular to the second direction.

17. The process of claim 16, wherein the first direction is a horizontal direction when the first and second poles of the quadrupole lens are vertically aligned, and the second direction is a vertical direction when the third and fourth poles of the quadrupole lens are horizontally aligned.

18. The process of claim 16, wherein the first direction is a 135°

diagonal direction when the first and second poles of the quadrupole lens are 45°

diagonally aligned, and the second direction is a 45°

diagonal direction when the third and fourth poles of the quadrupole lens are 135°

diagonally aligned.

19. A manufacturing aware process for designing an integrated circuit (“

IC”

) layout, the process comprising;

specifying an off-axis illumination configuration for the IC layout;

at a computing device, defining a wiring configuration based on the specified illumination configuration; and

using the defined wiring configuration to route the IC layout.

20. The process of claim 19, wherein the specified off-axis illumination configuration comprises a lens and a light source that strikes a surface of the lens not at a perpendicular angle.

21. The process of claim 19, wherein defining the wiring configuration comprises defining a first width for a first route and a second width for a second route for each layer of the IC layout based on the specified off-axis illumination configuration.

22. The process of claim 19, wherein defining the wiring configuration comprises:

identifying a first spacing constraint for routes in a first plurality of routes along a first direction of a first layer of the IC layout; and

identifying a second spacing constraint for routes in a second plurality of routes along a second direction of the first layer of the IC layout.

23. The process of claim 22, wherein the first spacing constraint is narrower than the second spacing constraint.

24. A non-transitory computer readable medium storing a computer program for execution by at least one processor, the computer program for designing an integrated circuit (“

IC”

) layout, the computer program comprising sets of instructions for;

specifying a stepper lens for a particular layer of the IC layout as part of an illumination configuration;

defining a wiring configuration based on the illumination configuration; and

using the defined wiring configuration to route the IC layout.

25. The non-transitory computer readable medium of claim 24, wherein the specified stepper lens is one of a dipole lens and a quadrupole lens.

26. The non-transitory computer readable medium of claim 24, wherein the set of instructions for defining the wiring configuration comprises a set of instructions for defining a first width for a first route and a second width for a second route for at least one layer of the IC layout based on the specified stepper lens.

27. The non-transitory computer readable medium of claim 24, wherein the specified stepper lens is a quadrupole lens comprising four poles, wherein the set of instructions for defining the wiring configuration comprises a set of instructions for defining a narrow route in a first direction, a narrow route in a second direction, and a wide route in a third direction different from the first and second directions for the IC layout when the first and second poles of the quadrupole lens are aligned in a direction that is perpendicular to the first direction, and the third and fourth poles of the quadrupole lens are aligned in a direction that is perpendicular to the second direction.

28. The non-transitory computer readable medium of claim 24, wherein the specified stepper lens is a dipole lens comprising two poles, wherein the set of instructions for defining the wiring configuration comprises a set of instructions for defining a narrow route in a first direction and a wide route in a second direction different from the first direction for the IC layout when the two poles of the dipole lens are aligned in a direction that is perpendicular to the first direction.

29. The non-transitory computer readable medium of claim 28, wherein the first direction is a horizontal direction when the two poles of the dipole lens are vertically aligned.

30. The non-transitory computer readable medium of claim 28, wherein the first direction is a 135°

diagonal direction when the two poles of the dipole lens are 45°

diagonally aligned.

31. A system comprising:

at least one processor for executing sets of instructions; and

a memory storing a computer program for designing an integrated circuit (“

IC”

) layout, the computer program comprising sets of instructions to be executed in the processor for;

specifying an off-axis illumination configuration for the IC layout;

defining a wiring configuration based on the specified illumination configuration; and

using the defined wiring configuration to route the IC layout.

32. The system of 31, wherein the specified off-axis illumination configuration comprises a lens and a light source that strikes a surface of the lens not at a perpendicular angle.

33. The system of 31, wherein the set of instructions for defining the wiring configuration comprises a set of instructions for defining a first width for a first route and a second width for a second route for each layer of the IC layout based on the specified off-axis illumination configuration.

34. The system of 31, wherein the set of instructions for defining the wiring configuration comprises sets of instructions for:

identifying a first spacing constraint for routes in a first plurality of routes along a first direction of a first layer of the IC layout; and

identifying a second spacing constraint for routes in a second plurality of routes along a second direction of the first layer of the IC layout.