Wafer and manufacturing method of electronic component

• US 8,021,712 B2
• Filed: 03/18/2009
• Issued: 09/20/2011
• Est. Priority Date: 03/18/2009
• Status: Expired due to Fees

• Current Assignee: TDK Corporation
• Original Assignee: TDK Corporation
• Inventors: Nakazawa, Osamu, Hachisuka, Nozomu, Hiraki, Tetsuya
• Primary Examiner(s): BERNATZ, KEVIN M
• Application Number:
  US12/406,445
• Publication Number:
  US 20100237345A1
• Time in Patent Office: 916 Days
• Field of Search: None
• US Class Current: 427/97.6
• CPC Class Codes: G11B 5/00817 on longitudinal tracks only, e.g. for serpentine format recording
• CPC Class Codes: G11B 5/3993 in semi-conductors
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: Y10T 428/24355 Continuous and nonuniform or irregular surface on layer or component [e.g., roofing, etc.]

Abstract

The present invention relates to a wafer formed with an evaluation element and capable of improving productivity and a manufacturing method of an electronic component using the same. In a wafer according to the present invention, a plurality of elements connected to electrode films through lead-out conductive films are arranged and a chip area is defined for cutting out the plurality of elements in a given number. In the wafer, at least one evaluation element is formed in an area outside the chip area. The lead-out conductive films extend to the outside area and are connected to the evaluation elements. With this wafer, since the lead-out conductor is shared between the element and the evaluation element, the electrode film connected therewith can be shared, too. Accordingly, evaluation can be performed by using the evaluation element without the need of providing the wafer with a lead-out conductor and an electrode film exclusively for the evaluation element, so that the chip area to be cut out from the wafer can be made larger than before.

Claims

1. A wafer comprising:

a chip area; and

an outside area of said chip area, wherein

said chip area includes a plurality of chips arranged therein,

each of said plurality of chips includes one or more elements, electrode films, and lead-out conductive films,

each of said one or more elements is connected to said electrode films through said lead-out conductive films within each of said plurality of chips,

only said outside area includes at least one evaluation element, and

said lead-out conductive films extend to said outside area and are connected to said at least one evaluation element said one or more elements and said electrode films are located in said chip area, without being located outside said chip area, and

Said at least one evaluation element is electrically connected to one of said electrode films such that said at least one evaluation element is capable of providing evaluation characteristics via said one of said electrode films.

2. The wafer of claim 1, wherein said one or more elements are arranged along a boundary between said chip area and said outside area.

3. The wafer of claim 1, wherein said one or more elements are arranged at regular intervals.

4. The wafer of claim 1, wherein each of said or more elements has a pair of opposed first terminals,

said lead-out conductive films and said electrode films are formed for each of said first terminals, and

said first terminals are connected to said electrode films through said lead-out conductive films.

5. The wafer of claim 4, wherein said at least one evaluation element has a pair of opposed second terminals, and

said pair of second terminals are connected through said lead-out conductive films to different ones of said first terminals that are disposed at two different elements of said one or more elements.

6. The wafer of claim 5, wherein said two different elements are disposed adjacent to each other.

7. The wafer of claim 6, wherein said pair of second terminals are connected to each of two said first terminals that are disposed adjacent to each other.

8. The wafer of claim 1, wherein a plurality of said at least one evaluation element is arranged along a boundary between said chip area and said outside area.

9. The wafer of claim 8, wherein said plurality of said at least one evaluation element is arranged at regular intervals.

10. The wafer of claim 1, wherein said chip area is to be used for manufacturing a magnetic head, and

each of said one or more elements is a magneto-resistive effect element and formed in such a manner as to be partially exposed on a section when said chip area is cut out.

11. The wafer of claim 10, wherein dimensions of a plurality of said at least one evaluation element in a direction perpendicular to said section are different from each other.

12. The wafer of claim 10, wherein said at least one evaluation element has smaller dimensions than said one or more elements in a direction perpendicular to said section.

13. The wafer of claim 1, wherein contact areas of a plurality of said at least one evaluation element with said lead-out conductive films are different from each other.

14. The wafer of claim 1, wherein areas of a plurality of said at least one evaluation element in a layer plane are different from each other.

15. The wafer of claim 1, wherein at least some of a plurality of said at least one evaluation element are connected to each other through a conductive film.

16. A manufacturing method of an electronic component using a wafer having a chip area and an outside area of said chip area, wherein

said chip area includes a plurality of chips arranged therein,

each of said plurality of chips includes one or more elements, electrode films, and lead-out conductive films,

each of said one or more elements is connected to said electrode films through said lead-out conductive films within each of said plurality of chips,

only said outside area includes at least one evaluation element,

said lead-out conductive films extend to said outside area and are connected to said at least one evaluation element said one or more elements and said electrode films are located in said chip area, without being located outside said chip area,

the method comprising the steps of:

evaluating characteristics of said at least one evaluation element via said electrode films;

cutting out said chip area from said wafer to remove said outside area; and

dicing said chip area to obtain each of said plurality of chips as an electronic component.

17. The electronic component manufacturing method of claim 16, wherein said one or more elements are arranged along a boundary between said chip area and said outside area.

18. The electronic component manufacturing method of claim 16, wherein said one or more elements are arranged at regular intervals.

19. The electronic component manufacturing method of claim 16, wherein each of said one or more elements has a pair of opposed first terminals, and

said first terminals are connected to said electrode films through said lead-out conductive films.

20. The electronic component manufacturing method of claim 19, wherein said at least one evaluation element has a pair of opposed second terminals, and

said pair of second terminals are connected through said lead-out conductive films to different ones of said first terminals that are disposed at two different elements of said one or more elements.

21. The electronic component manufacturing method of claim 20, wherein said two different elements are disposed adjacent to each other.

22. The electronic component manufacturing method of claim 21, wherein said pair of second terminals are connected to each of two said first terminals that are disposed adjacent to each other.

23. The electronic component manufacturing method of claim 16, wherein a plurality of said at least one evaluation element is arranged along a boundary between said chip area and said outside area.

24. The electronic component manufacturing method of claim 23, wherein said plurality of said at least one evaluation element is arranged at regular intervals.

25. The electronic component manufacturing method of claim 16, wherein said chip area is to be used for manufacturing a magnetic head, and

each of said one or more elements is a magneto-resistive effect element and formed in such a manner as to be partially exposed on a section when said chip area is cut out.

26. The electronic component manufacturing method of claim 25, wherein dimensions of a plurality of said at least one evaluation element in a direction perpendicular to said section are different from each other.

27. The electronic component manufacturing method of claim 25, wherein said at least one evaluation element has smaller dimensions than said one or more elements in a direction perpendicular to said section.

28. The electronic component manufacturing method of claim 16, wherein contact areas of a plurality of said at least one evaluation element with said lead-out conductive films are different from each other.

29. The electronic component manufacturing method of claim 16, wherein areas of a plurality of said at least one evaluation element in a layer plane are different from each other.

30. The electronic component manufacturing method of claim 16, wherein at least some of a plurality of said at least one evaluation element are connected to each other through a conductive film.