Multi-chip reticle photomasks

• US 8,021,803 B2
• Filed: 06/12/2009
• Issued: 09/20/2011
• Est. Priority Date: 06/12/2009
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Rankin, Jed Hickory, Anderson, Brent Alan
• Primary Examiner(s): ROSASCO, STEPHEN D
• Application Number:
  US12/483,414
• Publication Number:
  US 20100316938A1
• Time in Patent Office: 830 Days
• Field of Search: 430/5, 430/394, 716 50- 55
• US Class Current: 430/5
• CPC Class Codes: G03F 1/26 Phase shift masks [PSM]; PSM blanks; Preparation thereof
• CPC Class Codes: G03F 1/50 Mask blanks not covered by G03F1/20 - G03F1/34; Preparation thereof

Abstract

A multi-chip reticle, methods of designing and fabricating multi-chip reticles, a system for designing a multi-chip reticle, and a method of fabricating integrated circuit chips using the multi-chip reticle. The multi-chip reticle includes a transparent substrate having two or more separate chip images arranged in an array, each chip image of said two or more chip images having only one type of reticle image, wherein at least two of said two more chip images have different types of reticle images.

Claims

1. A multi-chip reticle, comprising:

a transparent substrate having separate two or more chip images arranged in an array, each chip image of said two or more chip images being different, each chip image of said two or more chip images having only one type of reticle image, wherein at least two of said two or more chip images consist of different types of reticle images, each type of reticle image having a different physical structure.

2. The multi-chip reticle of claim 1, wherein said types of reticle images are selected from the group consisting of positive phase shift reticle images, negative phase shift reticle images, attenuated phase shift reticle images, embedded attenuated phase shift reticle images, alternating phase shift reticle images and binary alternating phase shift reticle images.

3. The multi-chip reticle of claim 1, wherein each chip image of said two or more chip images define different fabrication levels of a same integrated circuit chip design.

4. The multi-chip reticle of claim 1, wherein at least two chip images of said two or more chip images define a same fabrication level of integrated circuit chips of different design.

5. The multi-chip reticle of claim 1, wherein at least two chip images of said two or more chip images in combination define a same fabrication level of a same integrated circuit chip design.

6. The multi-chip reticle of claim 1, wherein said chip images define fabrication levels of a field effect transistor, said fabrication levels selected from the group consisting of trench dielectric isolation fabrication levels, gate fabrication levels, contact fabrication dielectric layers, metal wiring fabrication levels and via fabrication levels.

7. The multi-chip reticle of claim 1, wherein said types of reticle images are selected from the group consisting of binary reticle images, positive phase shift reticle images, negative phase shift reticle images, attenuated phase shift reticle images, embedded attenuated phase shift reticle images, alternating phase shift reticle images and binary alternating phase shift reticle images.

8. The multi-chip reticle of claim 7, wherein:

said binary reticle images consisting of the structure of a first polygon of a partial transmittance material on a transparent substrate and a second polygon of an opaque material on a top surface of said first polygon, said first and second polygons coextensive;

said positive phase shift reticle images consisting of the structure of a first polygon of a partial transmittance material on a transparent substrate and a second polygon of an opaque material on a top surface of said first polygon, a perimeter of said second polygons completely within a perimeter of said first polygon;

said negative phase shift reticle images consisting of the structure a first polygon of a partial transmittance material on a transparent substrate and a second polygon of an opaque material on a top surface of said first polygon, a perimeters of said first and second polygons coextensive and an opening in said second polygon in which a top surface of said first polygon is exposed;

said attenuated phase shift reticle images consisting of the structure a first polygon of a partial transmittance material on a transparent substrate;

said embedded attenuated phase shift reticle images consisting of the structure a polygon of a partial transmittance material on a transparent substrate and a trench in said substrate adjacent to and surrounding said polygon;

said alternating phase shift reticle images consisting of the structure a polygon of a said substrate surrounded by a trench in said substrate; and

said binary alternating phase shift reticle images consisting of a first polygon of a partial transmittance material on a transparent substrate and a second polygon of an opaque material on a top surface of said first polygon, said first and second polygons coextensive and a trench in said substrate adjacent to and surrounding said first polygon.

9. A method of forming a multi-chip reticle, comprising:

providing a transparent substrate; and

forming separate two or more chip images arranged in an array on said substrate, each chip image of said two or more chip images being different, each chip image of said two or more chip images having only one type of reticle image, wherein at least two of said two or more chip images consist of different types of reticle images, each type of reticle image having a different physical structure.

10. The method of claim 9, wherein said types of reticle images are selected from the group consisting of positive phase shift reticle images, negative phase shift reticle images, attenuated phase shift reticle images, embedded attenuated phase shift reticle images, alternating phase shift reticle images and binary alternating phase shift reticle images.

11. The method of claim 9, wherein said forming said two or more separate chip images includes:

forming binary reticle images in a selected chip image of said two or more chip images, said binary reticle images consisting of an opaque layer on a top surface of and coextensive with a partial transmittance layer, a bottom surface of said partial transmittance layer on a top surface of said substrate; and

forming positive phase shift reticle images in said selected chip image by removing a peripheral region of said opaque layer from binary reticle images in said selected chip image.

12. The method of claim 9, wherein said forming said two or more separate chip images includes:

forming binary reticle images in a selected chip image of said two or more chip images, said binary reticle images consisting of an opaque layer on a top surface of and coextensive with a partial transmittance layer, a bottom surface of said partial transmittance layer on a top surface of said substrate; and

forming embedded attenuated phase shift reticle images in said selected chip image by completely removing said opaque layer from said ef binary reticle images in said selected chip image followed by forming a trench in said substrate surrounding and immediately adjacent to sides of said partial transmittance layer in said selected chip image.

13. The method of claim 9, wherein said forming said two or more separate chip images includes:

forming binary reticle images in a selected chip image of said two or more chip images, said binary reticle images consisting of an opaque layer on a top surface of and coextensive with a partial transmittance layer, a bottom surface of said partial transmittance layer on a top surface of said substrate; and

forming alternating phase shift reticle images in said selected chip image by completely removing said opaque layer from said of binary reticle images in said selected chip image followed by forming a trench in said substrate surrounding and immediately adjacent to sides of said partial transmittance layer in said selected chip image followed by completely removing said partial transmittance layer in said selected chip image.

14. The method of claim 9, wherein said forming said two or more separate chip images includes:

forming binary reticle images in a selected chip image of said two or more chip images, said binary reticle images consisting of an opaque layer on a top surface of and coextensive with a partial transmittance layer, a bottom surface of said partial transmittance layer on a top surface of said substrate; and

forming positive binary alternating phase shift reticle images in said selected chip image by forming a trench in said substrate surrounding and immediately adjacent to sides of said partial transmittance layer in said selected chip image.

15. The method of claim 10, wherein said chip images define fabrication levels of a field effect transistor, said fabrication levels selected from the group consisting of trench dielectric isolation fabrication levels, gate fabrication levels, contact fabrication dielectric layers, metal wiring fabrication levels and via fabrication levels.

16. The multi-chip reticle of claim 9, wherein said types of reticle images are selected from the group consisting of binary reticle images, positive phase shift reticle images, negative phase shift reticle images, attenuated phase shift reticle images, embedded attenuated phase shift reticle images, alternating phase shift reticle images and binary alternating phase shift reticle images.

17. The method of claim 9, wherein said forming said two or more separate chip images includes:

forming binary reticle images in a selected chip image of said two or more chip images, said binary reticle images consisting of an opaque layer on a top surface of and coextensive with a partial transmittance layer, a bottom surface of said partial transmittance layer on a top surface of said substrate; and

forming negative phase shift reticle images in said selected chip image by removing central regions of said opaque layer of said binary reticle images in said selected chip image.

18. The method of claim 9, wherein said forming said two or more separate chip images includes:

forming binary reticle images in a selected chip image of said two or more chip images, said binary reticle images consisting of an opaque layer on a top surface of and coextensive with a partial transmittance layer, a bottom surface of said partial transmittance layer on a top surface of said substrate; and

forming attenuated phase shift reticle images in said selected chip image by completely removing said opaque layer from said binary reticle images in said selected chip image.