Methods of fabricating a cross point memory array

• US 8,021,897 B2
• Filed: 02/19/2009
• Issued: 09/20/2011
• Est. Priority Date: 02/19/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sandhu, Gurtej S., Sills, Scott
• Primary Examiner(s): Chambliss; Alonzo
• Application Number:
  US12/389,142
• Publication Number:
  US 20100207168A1
• Time in Patent Office: 943 Days
• Field of Search: None
• US Class Current: 438/3
• CPC Class Codes: H10B 63/22 of the metal-insulator-metal type
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays

Abstract

Some embodiments include cross-point memory structures. The structures may include a line of first electrode material extending along a first horizontal direction, a multi-sided container of access device materials over the first electrode material, a memory element material within the multi-sided container, and a line of second electrode material over the memory element material and extending along a second horizontal direction that is orthogonal to the first horizontal direction. Some embodiments include methods of forming memory arrays. The methods may include forming a memory cell stack over a first electrode material, and then patterning the first electrode material and the memory cell stack into a first set of spaced lines extending along a first horizontal direction. Spaced lines of second electrode material may be formed over the first set of spaced lines, and may extend along a second horizontal direction that is orthogonal to the first horizontal direction.

Claims

1. A method of forming a memory array, comprising:

forming first electrode material over a base;

forming a memory cell stack over the first electrode material;

the memory cell stack including, in ascending order from the first electrode material, a first insulator material, at least one additional insulator material, an electrically conductive material, and memory element material;

patterning the first electrode material and the memory cell stack into a first set of spaced lines extending primarily along a first horizontal direction;

forming dielectric material between the spaced lines of the first set;

forming spaced lines of second electrode material over the first set of spaced lines and over the dielectric material, the lines of second electrode material being a second set of spaced lines and extending primarily along a second horizontal direction that is orthogonal to the first horizontal direction; and

removing memory element material and electrically conductive material of the memory cell stack from regions between the lines of the second set to leave an array of memory unit cells, individual memory unit cells comprising the memory cell stack between the first electrode material and the second electrode material.

2. The method of claim 1 wherein the removing of the memory element material and the electrically conductive material of the cell stack occurs before forming the spaced lines of the second electrode material.

3. The method of claim 1 wherein the removing of the memory element material and the electrically conductive material of the cell stack occurs after forming the spaced lines of the second electrode material.

4. The method of claim 1 wherein the spaced lines of second electrode material are formed directly over the first set of spaced lines of the memory cell stack and utilized as an electrically conductive hard mask during the removing of the memory element material and the electrically conductive material of the memory stack.

5. The method of claim 1 further comprising:

forming a patterned mask over the first set of spaced lines and over the dielectric material, the patterned mask comprising spaced lines extending primarily along the second horizontal direction; and

forming the second electrode material within spaces between the spaced lines of the patterned mask to thereby form spaced lines of second electrode material.

6. The method of claim 5 wherein the dielectric material is a first dielectric material, and further comprising, after forming the second electrode material, replacing the spaced lines of the patterned mask with a second dielectric material.

7. The method of claim 6 wherein the second dielectric material is a same composition as the first dielectric material.

8. The method of claim 5 wherein the second electrode material is initially formed over the spaced lines of the patterned mask as well as between the spaced lines of the patterned mask, and further comprising planarizing the second electrode material to remove the second electrode material from over the spaced lines of the patterned mask, while leaving the second electrode material between the spaced lines of the patterned mask.

9. The method of claim 5 wherein the patterned mask is a second patterned mask, and wherein the patterning of the first electrode material and the memory cell stack into the first set of spaced lines, comprises:

forming a first patterned mask over the memory cell stack, the first patterned mask comprising a plurality of spaced lines extending along the first horizontal direction; and

transferring a pattern from the first patterned mask through the memory cell stack and the first electrode material with one or more etches.

10. The method of claim 9 wherein the first patterned mask remains over the first set of lines as the dielectric material is formed between the spaced lines of the first set.

11. The method of claim 9 wherein the first patterned mask comprises one or more of amorphous carbon, transparent carbon, silicon dioxide, silicon nitride and silicon oxynitride.

12. The method of claim 11 wherein the second patterned mask comprises one or more of amorphous carbon, transparent carbon, silicon dioxide, silicon nitride and silicon oxynitride.

13. The method of claim 1 wherein:

the first electrode material has a low work function relative to the electrically conductive material of the memory cell stack,

the first electrode material comprises one or more compositions selected from the group consisting of tantalum silicon nitride, chromium and tantalum, and

the electrically conductive material of the memory cell stack comprises one or more compositions selected from the group consisting of platinum, titanium nitride and tantalum nitride.

14. The method of claim 1 wherein one or more other components of the memory cell stack are removed from between the spaced lines of the second set in addition to the memory element material and the electrically conductive material.

15. The method of claim 1 wherein the only components of the memory cell stack that are removed from between the spaced lines of the second set are the memory element material and the electrically conductive material.

16. A method of forming a memory array, comprising:

forming a substrate to comprise a plurality of spaced apart lines of first electrode material, and to comprise trenches directly over the spaced apart lines and in one-to-one correspondence with the spaced apart lines;

the trenches and the lines of first electrode material extending along a first horizontal direction;

forming access device materials within the trenches to partially fill the trenches and thereby narrow the trenches, the access device materials including an electrically conductive metal-containing material and at least two insulative materials, the insulative materials being between the electrically conductive metal-containing material and the first electrode material;

forming memory element material within the narrowed trenches, the memory element material forming a plug that extends into the access device materials, and the access device materials extending along a bottom and two sides of the memory element plug, the memory element material being configured as a plurality of spaced apart lines in one-to-one correspondence with the trenches;

forming second electrode material over the memory element material lines and over regions between the spaced apart memory element lines;

forming a patterned mask over the second electrode material, the patterned mask comprising a plurality of spaced apart lines, the spaced apart lines of the patterned mask extending along a second horizontal direction that is orthogonal to the first horizontal direction of the lines of first electrode material; and

transferring a pattern from the patterned mask through the second electrode material, through the memory element material and through the access device materials to thereby pattern the access device materials and memory element material into array of memory cells, and to pattern the second electrode material into top electrode lines extending over the memory cells and orthogonally to the lines of first electrode material.

17. The method of claim 16 wherein the access device materials are initially formed within the trenches to comprise sidewall regions along sidewalls of the trenches, and to comprise bottom regions along bottoms of the trenches;

and further comprising recessing the sidewall regions of the access device materials to a level beneath an upper level of the trenches prior to forming the memory element material.

18. The method of claim 17 wherein the recessing forms a planarized upper surface across the access device materials.

19. The method of claim 16 wherein the patterned mask is a second patterned mask, and wherein:

the substrate comprises a base and a first patterned mask over the base;

the first patterned mask comprises a plurality of spaced apart lines; and

the trenches correspond to gaps between the spaced apart lines of the first patterned mask.

20. The method of claim 16 wherein the patterned mask is a second patterned mask, and wherein the forming the substrate comprises:

forming a first patterned mask over a base, the first patterned mask comprising a plurality of spaced apart lines, the spaced apart lines being separated from one another by gaps;

etching into the base to extend the gaps into the base; and

filling a lower region of the gaps with the first electrode material to form the lines of the first electrode material, and leaving an unfilled upper region of the gaps as the trenches over the lines of the first electrode material.

21. A method of forming a memory array, comprising:

forming a substrate to comprise a plurality of spaced apart lines of first electrode material, and to comprise a plurality of polygonal openings directly over the lines of first electrode material;

the polygonal openings being in many-to-one correspondence with the lines of first electrode material;

the lines of first electrode material extending along a first horizontal direction;

forming access device materials within the openings to partially fill the openings and thereby narrow the openings, the access device materials including an electrically conductive metal-containing material and at least two insulative materials, the insulative materials being between the electrically conductive metal-containing material and the first electrode material;

forming memory element material within the narrowed openings, the memory element material within each individual opening forming a plug that extends into the access device materials, and the access device materials within each individual opening extending along a bottom of a memory element plug and around three or more sides of the memory element plug, the memory element material being configured as a plurality of spaced apart structures in one-to-one correspondence with the openings;

forming second electrode material over the memory element material structures and over regions between the spaced apart memory element structures;

forming a patterned mask over the second electrode material, the patterned mask comprising a plurality of spaced apart lines, the spaced apart lines of the patterned mask extending along a second horizontal direction that is orthogonal to the first horizontal direction of the lines of first electrode material; and

transferring a pattern from the patterned mask through the second electrode material to pattern the second electrode material into top electrode lines extending over the memory element material and orthogonally to the lines of first electrode material.

22. The method of claim 21 wherein the access device materials are initially formed within the openings to comprise sidewall regions along sidewalls of the openings, and to comprise bottom regions along bottoms of the openings, and further comprising recessing the sidewall regions of the access device materials to a level beneath an upper level of the openings prior to forming the memory element material.

23. The method of claim 22 wherein the recessing forms a planarized upper surface across the access device materials.

24. The method of claim 21 wherein the patterned mask is a third patterned mask, and wherein:

the substrate comprises a base, a first patterned mask over the base, and a second patterned mask over the first patterned mask and over the base,

the first patterned mask comprises a plurality of spaced apart lines extending primarily along the first horizontal direction;

the second patterned mask comprises a plurality of spaced apart lines extending primarily along a second horizontal direction that is orthogonal to the first horizontal direction; and

the openings correspond to overlapping gaps between the spaced apart lines of the first patterned mask and between the spaced apart lines of the second patterned mask.

25. The method of claim 21 wherein the patterned mask is a third patterned mask, wherein the forming the substrate comprises:

forming a first patterned mask over a base, the first patterned mask comprising a plurality of spaced apart lines, the spaced apart lines extending primarily along the first horizontal direction and being separated from one another by first gaps;

etching into the base to extend the first gaps into the base;

filling a lower region of the gaps with the first electrode material to form the lines of the first electrode material, and leaving an unfilled upper region of the first gaps as trenches over the lines of the first electrode material; and

forming a second patterned mask over the first patterned mask and the base, the second patterned mask comprising a plurality of spaced apart lines, the spaced apart lines of the second patterned mask extending primarily along a second horizontal direction that is orthogonal to the first horizontal direction and being separated from one another by second gaps, and regions where the second gaps overlap with the first gaps being the polygonal openings.

26. The method of claim 25 wherein the first and second patterned masks comprise one or more of amorphous carbon, transparent carbon, silicon dioxide, silicon nitride and silicon oxynitride.

27. The method of claim 25 wherein the polygonal openings comprise four sides.