Remote chip attachment

• US 8,021,922 B2
• Filed: 06/25/2010
• Issued: 09/20/2011
• Est. Priority Date: 06/14/2005
• Status: Active Grant

• Current Assignee: Cufer Asset Ltd LLC (Intellectual Ventures LLC)
• Original Assignee: Cufer Asset Ltd LLC (Intellectual Ventures LLC)
• Inventors: Trezza, John
• Primary Examiner(s): POTTER, ROY KARL
• Application Number:
  US12/823,419
• Publication Number:
  US 20100261297A1
• Time in Patent Office: 452 Days
• Field of Search: 257/737, 257/738, 257/777, 257/723, 257/778, 438/15, 438/108, 438/613
• US Class Current: 438/108
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05023 the whole internal layer protruding from the surface
• CPC Class Codes: H01L 2224/05026 the internal layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/0508 being stacked
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05664 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/0615 Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13609 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/24226 : the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/75305 : comprising protrusions
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/75 : Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01025 : Manganese [Mn]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A method of attaching a pair of chips, each having primary contacts that can be mated to each other, involves forming one or more secondary contacts on each of the two chips of a shape sufficient to prevent an initial attachment material from contacting any of the primary contacts during a preliminary attachment operation, the secondary contacts further having a height that will prevent the primary contacts from touching when the secondary contacts are brought into contact with each other, bringing the secondary contacts into closer and closer aligned proximity to each other at least until the primary contacts touch in a first phase, and heating the primary contacts until material between each of corresponding primary contacts on each of the chips in the pair forms an electrical connection.

Claims

1. A method comprising:

forming a primary contact and a secondary contact on a first chip;

forming a primary contact and a secondary contact on a second chip;

bringing the first and second chips into proximity such that the secondary contacts of the first and second chips form an attachment during a first attachment phase, wherein the secondary contacts of the first and second chips have a combined height such that the primary contacts of the first and second contacts do not touch each other during the first attachment phase;

bringing the first and second chips into closer proximity during a second attachment phase such that the primary contacts of the first and second chips touch; and

heating the primary contacts of the first and second chips to form an electrical connection therebetween.

2. The method of claim 1, wherein the first attachment phase comprises squeezing the secondary contacts of the first and second chips together at room temperature to form an electrical connection.

3. The method of claim 1, wherein the secondary contacts are formed on a periphery of the first and second chips.

4. The method of claim 1, wherein the secondary contacts are configured to enable testing of the first and second chips, the method further comprising testing the chips using the secondary contacts of the first and second chips prior to said bringing the first and second chips into proximity.

5. The method of claim 1, wherein the secondary contacts are larger in width and height than the primary contacts.

6. The method of claim 1, wherein the secondary contacts of the first and second chips comprise a metal having a melting point below 250 degrees Celsius.

7. The method of claim 6, wherein the metal comprises indium.

8. The method of claim 6, wherein the metal comprises at least one of a solder or an alloy.

9. The method of claim 1, further comprising reflowing the primary contacts on the first and second chips to self-center the first and second chips.

10. The method of claim 1, wherein said bringing the first and second chips into proximity comprises forming a non-electrically-conductive well from the secondary contacts of the first and second chips.

11. The method of claim 10, wherein the non-electrically-conductive well comprises at least one of a dielectric material, a photoresist material, or an epoxy.

12. A method comprising:

aligning a first chip with a second chip, wherein the first chip includes a first primary contact and a first secondary contact, and wherein the second chip includes a second primary contact and a second secondary contact;

bringing the first and second chips into proximity such that the first and second secondary contacts form an attachment during a first attachment phase, wherein the first and second secondary contacts have a combined height such that the first and second primary contacts do not touch during the first attachment phase;

bringing the first and second chips into closer proximity during a second attachment phase such that the first and second primary contacts are brought together; and

heating the first and second primary contacts to form an electrical connection therebetween.

13. The method of claim 12, wherein the attachment between the first and second secondary contacts is formed by squeezing the secondary contacts of the first and second chips together at room temperature.

14. The method of claim 12, wherein the first and second secondary contacts are formed on a periphery of the first and second chips, respectively.

15. The method of claim 12, wherein the first and second secondary contacts are configured to allow testing of the first and second chips, respectively, the method further comprising testing the first and second chips using the first and second secondary contacts prior to said aligning a first chip with a second chip.

16. The method of claim 12, wherein the attachment between the first and second secondary contacts is configured to allow communication between the first and second chips and to allow testing of the first and second chips, the method further comprising testing the first and second chips using the attachment between the first and second secondary contacts after said bringing the first and second chips into proximity.

17. The method of claim 12, wherein the first and second secondary contacts are larger in width and height than the first and second primary contacts.

18. The method of claim 12, wherein the first and second secondary contacts comprise a conductive material having a melting point below 250 degrees Celsius.

19. The method of claim 18, wherein the conductive material comprises indium.

20. The method of claim 18, wherein the conductive material comprises a solder.

21. The method of claim 20, wherein the conductive material comprises an alloy.

22. The method of claim 12, wherein the first primary contact comprises a rigid post and the second primary contact is more malleable than the first primary contact, and wherein said bringing the first and second chips into closer proximity comprises penetrating the first primary contact into the second primary contact.

23. The method of claim 12, wherein the first and second secondary contacts are bonded to each other at room temperature by van der Waals forces.

24. The method of claim 12, wherein the first and second secondary contacts are bonded to each other by covalent bonding.

25. The method of claim 12, wherein the first primary contact is located on and electrically connected to an electrically-conductive via that extends into the first chip.

26. The method of claim 12, wherein the first and second secondary contacts form a non-electrically-conductive connection between the first and second chips.

27. A method comprising:

aligning a first chip with a second chip, wherein the first chip includes a first primary contact and a first remote contact, wherein the second chip includes a second primary contact and a second remote contact, and wherein the first remote contact comprises a rigid material and the second remote contact comprises a malleable material that is more malleable than the rigid material;

bringing the first and second chips into proximity such that the first and second remote contacts form an attachment during an initial attach phase, wherein the first and second remote contacts have a combined height such that the first and second primary contacts do not touch during the initial attach phase;

bringing the first and second chips into closer proximity during a subsequent fuse phase such that the first and second primary contacts are brought into contact; and

heating the first and second primary contacts to form an electrical connection therebetween.

28. The method of claim 27, wherein said bringing the first and second chips into proximity comprises penetrating the first remote contact into the second remote contact.

29. The method of claim 27, wherein the first and second remote contacts are formed on a periphery of the first and second chips, respectively.

30. The method of claim 27, wherein the first and second remote contacts are configured to enable testing of the first and second chips, respectively, the method further comprising testing the chips using the first and second remote contacts of the first and second chips prior to said aligning a first chip with a second chip.

31. The method of claim 27, further comprising testing the first and second chips using a pad formed in electrical connection with the attachment of the first and second remote contacts, wherein said testing the first and second chips is performed after said bringing the first and second chips into proximity.

32. The method of claim 27, wherein the first and second remote contacts of the first and second chips comprise an electrically-conductive material having a melting point below 250 degrees Celsius.

33. The method of claim 27, wherein the first and second remote contacts form a non-electrically-conductive well that comprises at least one of a dielectric material, a photoresist material, or an epoxy.

34. The method of claim 27, wherein the first primary contact comprises a rigid post and the second primary contact is malleable relative to the first primary contact, and wherein said bringing the first and second chips into closer proximity comprises penetrating the first primary contact into the second primary contact.

35. The method of claim 27, wherein the first primary contact is located on and electrically connected to an electrically-conductive via that extends into the first chip.