Method of wire bonding over active area of a semiconductor circuit

• US 8,021,976 B2
• Filed: 05/08/2003
• Issued: 09/20/2011
• Est. Priority Date: 10/15/2002
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Chen, Ying-chih, Lee, Jin-Yuan
• Primary Examiner(s): Wilson; Allan R
• Application Number:
  US10/434,142
• Publication Number:
  US 20040070042A1
• Time in Patent Office: 3,057 Days
• Field of Search: 438/612, 438/613, 438/614, 438/618, 438/623, 438/780, 438653-654, 438/627, 438/628, 257/E23.02, 257/751, 257/753, 257/E21.508, 257/E23.015
• US Class Current: 438/628
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05073 Single internal layer
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05187 Ceramics, e.g. crystalline carbides, nitrides or oxides glass ceramics H01L2224/05188
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/4807 of bonding interfaces, e.g. interlocking features
• CPC Class Codes: H01L 2224/48453 of the interface with the bonding area
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/48599 Principal constituent of the connecting portion of the wire connector being Gold (Au)
• CPC Class Codes: H01L 2224/48624 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48644 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48647 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/854 : with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/85424 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/85444 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/85447 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01007 : Nitrogen [N]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

Claims

1. A method for wirebonding to an integrated circuit die comprising:

providing a semiconductor substrate, an active device in or over said semiconductor substrate, a first interconnect metal layer over said semiconductor substrate, an intermetal dielectric layer over said first interconnect metal layer, a second interconnect metal layer over said intermetal dielectric layer, a passivation layer over said intermetal dielectric layer and over said second interconnect metal layer, wherein an opening in said passivation layer is over a first contact point of said second interconnect metal layer, and said first contact point is at a bottom of said opening, wherein said passivation layer comprises a nitride, and a third interconnect metal layer over said semiconductor substrate, wherein said third interconnect metal layer is connected to said first contact point through said opening, wherein said third interconnect metal layer comprises a titanium-containing layer, a gold seed layer on said titanium-containing layer, and an electroplated gold layer with a thickness greater than 1 micrometer on said gold seed layer; and

forming a wire bond on to a second contact point of said third interconnect metal layer, wherein said wire bond comprises a ball bond with a bottom contacting said second contact point, wherein said second contact point is connected to said first contact point through said opening, wherein a first contact area between said first contact point and said third interconnect metal layer has a width smaller than that of a second contact area between said second contact point and said ball bond, wherein said second contact area is vertically over said active device, vertically over a first metal interconnect of said first interconnect metal layer and vertically over a second metal interconnect of said second interconnect metal layer, wherein said second contact area is further vertically over a first sidewall of said first metal interconnect and vertically over a second sidewall of said first metal interconnect, wherein said first sidewall is opposite to said second sidewall, and wherein said second contact area is further vertically over a third sidewall of said second metal interconnect and vertically over a fourth sidewall of said second metal interconnect, wherein said third sidewall is opposite to said fourth sidewall.

2. The method of claim 1, wherein said titanium-containing layer comprises a titanium-tungsten-alloy layer.

3. The method of claim 1, wherein said titanium-containing layer comprises a titanium-nitride layer.

4. The method of claim 1, wherein said intermetal dielectric layer has a dielectric constant less than 3.0.

5. The method of claim 1, wherein said intermetal dielectric layer comprises fluorinated silicate glass (FSG).

6. The method of claim 1 further comprising providing a polymer layer over said passivation layer.

7. The method of claim 1 further comprising providing a polymer layer on said passivation layer, wherein said third interconnect metal layer is further on said polymer layer.

8. The method of claim 1 further comprising providing a polymer layer on said passivation layer, wherein said third interconnect metal layer is further on said polymer layer, and said second contact area is further vertically over a portion of said polymer layer.

9. The method of claim 1, wherein said providing said third interconnect metal layer comprises annealing said electroplated gold layer at a temperature between 120 and 350 degrees C. in a nitrogen ambient.

10. The method of claim 1, wherein said providing said third interconnect metal layer comprises annealing said electroplated gold layer.

11. The method of claim 1, wherein said providing said third interconnect metal layer comprises annealing said electroplated gold layer at a temperature between 120 and 350 degrees C.

12. The method of claim 1, wherein said intermetal dielectric layer comprises silicon, oxygen and carbon.

13. A method for wirebonding to an integrated circuit die comprising:

providing a semiconductor substrate, an active device in or over said semiconductor substrate, a first interconnect metal layer over said semiconductor substrate, an intermetal dielectric layer over said first interconnect metal layer, a second interconnect metal layer over said intermetal dielectric layer, a passivation layer over said intermetal dielectric layer and over said second interconnect metal layer, wherein an opening in said passivation layer is over a first contact point of said second interconnect metal layer, and said first contact point is at a bottom of said opening, wherein said passivation layer comprises a nitride, and a third interconnect metal layer on said first contact point and over said passivation layer, wherein said third interconnect metal layer is connected to said first contact point through said opening, wherein said third interconnect metal layer comprises a titanium-containing layer, a gold seed layer on said titanium-containing layer, and an electroplated gold layer with a thickness greater than 1 micrometer on said gold seed layer; and

forming a wire bond on to a second contact point of said third interconnect metal layer, wherein said wire bond comprises a ball bond with a bottom contacting said second contact point, wherein said second contact point is connected to said first contact point through said opening, wherein a first contact area between said first contact point and said third interconnect metal layer has a width smaller than that of a second contact area between said second contact point and said ball bond, wherein said second contact area is vertically over said active device, vertically over said opening, vertically over said first contact area, vertically over a portion of said passivation layer, vertically over a first metal interconnect of said first interconnect metal layer and vertically over a second metal interconnect of said second interconnect metal layer, wherein said second contact area is further vertically over a first sidewall of said opening and vertically over a second sidewall of said opening, wherein said first sidewall is opposite to said second sidewall, wherein said second contact area is further vertically over a third sidewall of said first metal interconnect and vertically over a fourth sidewall of said first metal interconnect, wherein said third sidewall is opposite to said fourth sidewall, and wherein said second contact area is further vertically over a fifth sidewall of said second metal interconnect and vertically over a sixth sidewall of said second metal interconnect, wherein said fifth sidewall is opposite to said sixth sidewall.

14. The method of claim 13, wherein said titanium-containing layer comprises a titanium-tungsten-alloy layer.

15. The method of claim 13, wherein said titanium-containing layer comprises a titanium-nitride layer.

16. The method of claim 13, wherein said intermetal dielectric layer has a dielectric constant less than 3.0.

17. The method of claim 13, wherein said intermetal dielectric layer comprises fluorinated silicate glass (FSG).

18. The method of claim 13 further comprising providing a polymer layer over said passivation layer.

19. The method of claim 13 further comprising providing a polymer layer on said passivation layer, wherein said third interconnect metal layer is further on said polymer layer.

20. The method of claim 13 further comprising providing a polymer layer on said passivation layer, wherein said third interconnect metal layer is further on said polymer layer, and said second contact area is further vertically over a portion of said polymer layer.

21. The method of claim 13, wherein said providing said third interconnect metal layer comprises annealing said electroplated gold layer at a temperature between 120 and 350 degrees C. in a nitrogen ambient.

22. The method of claim 13, wherein said providing said third interconnect metal layer comprises annealing said electroplated gold layer.

23. The method of claim 13, wherein said providing said third interconnect metal layer comprises annealing said electroplated gold layer at a temperature between 120 and 350 degrees C.

24. The method of claim 13, wherein said intermetal dielectric layer comprises silicon, oxygen and carbon.

25. A method for wirebonding to an integrated circuit die, comprising:

providing a semiconductor substrate, an active device in or over said semiconductor substrate, a first interconnect metal layer over said semiconductor substrate, an intermetal dielectric layer over said first interconnect metal layer, a second interconnect metal layer over said intermetal dielectric layer, and a passivation layer over said intermetal dielectric layer and over said second interconnect metal layer, wherein an opening in said passivation layer is over a first contact point of said second interconnect metal layer, and said first contact point is at a bottom of said opening, wherein said passivation layer comprises a nitride, and a third interconnect metal layer on said first contact point and over said passivation layer, wherein said third interconnect metal layer is connected to said first contact point through said opening, wherein said third interconnect metal layer comprises a titanium-containing layer, a gold seed layer on said titanium-containing layer, and an electroplated gold layer with a thickness greater than 1 micrometer on said gold seed layer; and

forming a wire bond on to a second contact point of said third interconnect metal layer, wherein said wire bond comprises a ball bond with a bottom contacting said second contact point, wherein said second contact point is connected to said first contact point through said opening, wherein a first contact area between said first contact point and said third interconnect metal layer has a width smaller than that of a second contact area between said second contact point and said ball bond, wherein said second contact area is vertically over said active device, vertically over a first metal interconnect of said first interconnect metal layer, vertically over a second metal interconnect of said second interconnect metal layer and vertically over a portion of said passivation layer, wherein said second contact area is further vertically over a first sidewall of said first metal interconnect and vertically over a second sidewall of said first metal interconnect, wherein said first sidewall is opposite to said second sidewall, and wherein said second contact area is further vertically over a third sidewall of said second metal interconnect and vertically over a fourth sidewall of said second metal interconnect, wherein said third sidewall is opposite to said fourth sidewall.

26. The method of claim 25, wherein said titanium-containing layer comprises a titanium-tungsten-alloy layer.

27. The method of claim 25, wherein said titanium-containing layer comprises a titanium-nitride layer.

28. The method of claim 25, wherein said intermetal dielectric layer has a dielectric constant less than 3.0.

29. The method of claim 25, wherein said intermetal dielectric layer comprises fluorinated silicate glass (FSG).

30. The method of claim 25 further comprising providing a polymer layer over said passivation layer.

31. The method of claim 25 further comprising providing a polymer layer on said passivation layer, wherein said third interconnect metal layer is further on said polymer layer.

32. The method of claim 25 further comprising providing a polymer layer on said passivation layer, wherein said third interconnect metal layer is further on said polymer layer, and said second contact area is further vertically over a portion of said polymer layer.

33. The method of claim 25, wherein said providing said third interconnect metal layer comprises annealing said electroplated gold layer at a temperature between 120 and 350 degrees C. in a nitrogen ambient.

34. The method of claim 25, wherein said providing said third interconnect metal layer comprises annealing said electroplated gold layer.

35. The method of claim 25, wherein said providing said third interconnect metal layer comprises annealing said electroplated gold layer at a temperature between 120 and 350 degrees C.

36. The method of claim 25, wherein said intermetal dielectric layer comprises silicon, oxygen and carbon.

37. A method for wirebonding to an integrated circuit die, comprising:

providing a semiconductor substrate, an active device in or over said semiconductor substrate, a first interconnect metal layer over said semiconductor substrate, an intermetal dielectric layer over said first interconnect metal layer, a second interconnect metal layer over said intermetal dielectric layer, a passivation layer over said intermetal dielectric layer and over said second interconnect metal layer, wherein a first opening in said passivation layer is over a first contact point of a first metal interconnect of said second interconnect metal layer, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of a second metal interconnect of said second interconnect metal layer, and said second contact point is at a bottom of said second opening, wherein said first metal interconnect has a portion spaced apart from said second metal interconnect, wherein said passivation layer comprises a nitride, and a third interconnect metal layer over said passivation layer and on said first and second contact points, wherein said first contact point is connected to said second contact point through said third interconnect metal layer, wherein said third interconnect metal layer comprises a titanium-containing layer a gold seed layer on said titanium-containing layer, and an electroplated gold layer with a thickness greater than 1 micrometer on said gold seed layer; and

forming a wire bond on a third contact point of said third interconnect metal layer, wherein said wire bond comprises a ball bond with a bottom contacting said third contact point, wherein said third contact point is connected to said first contact point through said first opening, and said third contact point is connected to said second contact point through said second opening, wherein a first contact area between said first contact point and said third interconnect metal layer has a first width smaller than a second width of a second contact area between said third contact point and said ball bond, wherein said second contact area is vertically over said active device, vertically over a third metal interconnect of said first interconnect metal layer and vertically over a fourth metal interconnect of said second interconnect metal layer, wherein said second contact area is further vertically over a first sidewall of said third metal interconnect and vertically over a second sidewall of said third metal interconnect, wherein said first sidewall is opposite to said second sidewall, and wherein said second contact area is further vertically over a third sidewall of said fourth metal interconnect and vertically over a fourth sidewall of said fourth metal interconnect, wherein said third sidewall is opposite to said fourth sidewall.

38. The method of claim 37, wherein said second contact area is further vertically over a portion of said passivation layer.

39. The method of claim 37, wherein said second contact area is further vertically over said first and second contact points.

40. The method of claim 37 further comprising said forming said wire bond with said second contact area is further vertically over said first contact point, vertically over a fifth sidewall of said first opening and vertically over a sixth sidewall of said first opening, wherein said fifth sidewall is opposite to said sixth sidewall.

41. The method of claim 37 further comprising said forming said wire bond with said second contact area having said second width greater than said first width plus a third width of a third contact area between said second contact point and said third interconnect metal layer.

42. The method of claim 37, wherein said titanium-containing layer comprises a titanium-tungsten-alloy layer.

43. The method of claim 37, wherein said titanium-containing layer comprises a titanium-nitride layer.

44. The method of claim 37, wherein said intermetal dielectric layer has a dielectric constant less than 3.0.

45. The method of claim 37, wherein said intermetal dielectric layer comprises fluorinated silicate glass (FSG).

46. The method of claim 37, wherein said providing said third interconnect metal layer comprises annealing said electroplated gold layer at a temperature between 120 and 350 degrees C. in a nitrogen ambient.

47. The method of claim 37, wherein said providing said third interconnect metal layer comprises annealing said electroplated gold layer.

48. The method of claim 37, wherein said providing said third interconnect metal layer comprises annealing said electroplated gold layer at a temperature between 120 and 350 degrees C.

49. The method of claim 37, wherein said second metal interconnect has a portion spaced apart from said portion of said first metal interconnect, wherein said portion of said first metal interconnect comprises said first contact point, and wherein said portion of said second metal interconnect comprises said second contact point.

50. The method of claim 37, wherein said intermetal dielectric layer comprises silicon, oxygen and carbon.