Thin-film transistor display panel and method of fabricating the same

• US 8,022,411 B2
• Filed: 07/07/2009
• Issued: 09/20/2011
• Est. Priority Date: 09/09/2008
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Ki-Won, Lee, Woo-Geun, Yang, Sung-Hoon, Yoon, Kap-Soo, Kim, Sung-Ryul
• Primary Examiner(s): HA, NATHAN W
• Application Number:
  US12/499,009
• Publication Number:
  US 20100059745A1
• Time in Patent Office: 805 Days
• Field of Search: 257/59, 257 69- 73, 257/E33.053, 438/151
• US Class Current: 257/72
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Provided are a thin-film transistor (TFT) display panel having improved electrical properties that can be fabricated time-effectively and a method of fabricating the TFT display panel. The TFT display panel includes: gate wirings which are formed on an insulating substrate; oxide active layer patterns which are formed on the gate wirings; data wirings which are formed on the oxide active layer patterns to cross the gate wirings; a passivation layer which is formed on the oxide active layer patterns and the data wirings and is made of silicon nitride (SiNx); and a pixel electrode which is formed on the passivation layer.

Claims

1. A thin-film transistor (TFT) display panel comprising:

gate wirings formed on an insulating substrate;

oxide active layer patterns formed on the gate wirings;

data wirings formed on the oxide active layer patterns to cross the gate wirings, the data wirings contacting the oxide active layer patterns;

a passivation layer formed on the oxide active layer patterns and the data wirings, wherein the passivation layer is made of silicon nitride (SiNx); and

a pixel electrode which is formed on the passivation layer.

2. The display panel of claim 1, wherein

the gate wirings include at least a gate wiring component, the gate wiring component including at least a first conductive layer and a second conductive layer, the first conductive layer having lower resistivity than the second conductive layer, the second conductive layer having superior contact characteristics with at least one of zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO) than the first conductive layer, and

the passivation layer is made of SiNx which does not contain hydrogen.

3. The display panel of claim 1, wherein each of the oxide active layer patterns is made of any material selected from ZnO, InZnO, InGaO, InSnO, ZnSnO, GaSnO, GaZnO, GaZnSnO, and GaInZnO.

4. A TFT display panel comprising:

gate wirings formed on an insulating substrate;

a gate insulating film which comprises a lower gate insulating film formed on the gate wirings and made of first SiNx and an upper gate insulating film formed on the lower gate insulating film and made of second SiNx;

oxide active layer patterns re formed on the gate insulating film;

data wirings formed on the oxide active layer patterns to cross the gate wirings, the data wirings contacting the oxide active layer patterns;

a passivation layer formed on the oxide active layer patterns and the data wirings; and

a pixel electrode formed on the passivation layer,

wherein the second SiNx contains a smaller amount of hydrogen than the first SiNx.

5. The display panel of claim 4, wherein

the gate wirings include at least a gate wiring component, the gate wiring component including at least a first conductive layer and a second conductive layer, the first conductive layer having lower resistivity than the second conductive layer, the second conductive layer having superior contact characteristics with at least one of zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO) than the first conductive layer, and

the second SiNx does not contain hydrogen.

6. The display panel of claim 4, wherein

the second conductive layer is a lower layer of the gate wiring component,

the first conductive layer is an upper layer of the gate wiring component, and

the passivation layer is made of SiNx.

7. The display panel of claim 6, wherein the passivation layer is made of SiNx which does not contain hydrogen.

8. The display panel of claim 4, wherein each of the oxide active layer patterns is made of any material selected from ZnO, InZnO, InGaO, InSnO, ZnSnO, GaSnO, GaZnO, GaZnSnO, and GaInZnO.

9. A method of fabricating a TFT display panel, the method comprising:

forming gate wirings on an insulating substrate;

forming oxide active layer patterns on the gate wirings;

forming data wirings on the oxide active layer patterns to cross the gate wirings, the data wirings contacting the oxide active layer patterns;

forming a passivation layer of SiNx on the oxide active layer patterns and the data wirings; and

forming a pixel electrode on the passivation layer.

10. The method of claim 9, wherein the passivation layer is formed by using a nitrogen (N.sub.2) gas, a helium (He) or argon (Ar) gas, and a silane (SiH.sub.4) gas as source gases, and a ratio of the combined flow rates of the N.sub.2 gas and the He or Ar gas to a flow rate of the SiH.sub.4 gas is about 28:

1 to 2000;

1.

11. The method of claim 10, wherein the passivation layer is formed under pressure conditions of 1500 to 5000 mTorr.

12. The method of claim 10, wherein the passivation layer is formed under electrical conditions of 290 to 920 W/m.sup.2.

13. The method of claim 10 further comprising:

forming at least a gate wiring component in the gate wirings;

forming at least a first conductive layer of the gate wiring component and a second conductive layer of the gate wiring component, the first conductive layer of the gate wiring component having lower resistivity than the second conductive layer of the gate wiring component, the second conductive layer of the gate wiring component having superior contact characteristics with at least one of zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO) than the first conductive layer of the gate wiring component,

wherein the passivation layer is made of SiNx which does not contain hydrogen.

14. A method of fabricating a TFT display panel, the method comprising:

forming gate wirings on an insulating substrate;

forming a lower gate insulating film, which is made of first SiNx, on the gate wirings and forming an upper gate insulating film, which is made of second SiNx, on the lower gate insulating film;

forming oxide active layer patterns on the gate insulating film;

forming data wirings on the oxide active layer patterns to cross the gate wirings, the data wirings contacting the oxide active layer patterns;

forming a passivation layer on the oxide active layer patterns and the data wirings; and

forming a pixel electrode on the passivation layer,

wherein the second SiNx contains a smaller amount of hydrogen than the first SiNx.

15. The method of claim 14, wherein the upper gate insulating film is formed by using an N.sub.2 gas, an He or Ar gas, and an SiH.sub.4 gas as source gases, and a ratio of the combined flow rates of the N.sub.2 gas and the He or Ar gas to a flow rate of the SiH.sub.4 gas is 28:

1 to 2000;

1.

16. The method of claim 15 further comprising:

forming at least a gate wiring component in the gate wirings;

forming at least a first conductive layer of the gate wiring component and a second conductive layer of the gate wiring component, the first conductive layer of the gate wiring component having lower resistivity than the second conductive layer of the gate wiring component, the second conductive layer of the gate wiring component having superior contact characteristics with at least one of zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO) than the first conductive layer of the gate wiring component,

wherein the upper gate insulating film is formed under pressure conditions of 1500 to 5000 mTorr.

17. The method of claim 15, wherein the upper gate insulating film is formed under electrical conditions of 290 to 920 W/m.sup.2.

18. The method of claim 15, wherein the lower gate insulating film is formed by using an ammonia gas and the SiH.sub.4 gas.

19. The method of claim 14, wherein the second SiNx does not contain hydrogen.

20. The method of claim 14, wherein the passivation layer is made of SiNx.

21. The method of claim 20, wherein the passivation layer is made of SiNx which does not contain hydrogen.