Checkerboarded high-voltage vertical transistor layout

• US 8,022,456 B2
• Filed: 11/01/2010
• Issued: 09/20/2011
• Est. Priority Date: 02/16/2007
• Status: Expired due to Fees

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Banerjee, Sujit, Parthasarathy, Vijay, Manley, Martin H.
• Primary Examiner(s): Bryant; Kiesha
• Assistant Examiner(s): Anya; Igwe U
• Application Number:
  US12/925,929
• Publication Number:
  US 20110089476A1
• Time in Patent Office: 323 Days
• Field of Search: 257/302, 257/E29.262
• US Class Current: 257/302
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0211 adapted for requirements of temperature
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged.

Claims

1. A transistor comprising:

a semiconductor die;

a plurality of transistor segments organized into a plurality of sections, each transistor segment having a length and a width, the length being substantially greater than the width, the transistor segments of each section being arranged in a side-by-side relationship along the width, each transistor segment including;

a pillar of a semiconductor material that extends in a vertical direction, the pillar having a source region disposed near a top surface, of the semiconductor die, an extended drain region, and a body region that vertically separates the source and extended drain regions;

first and second dielectric regions disposed on opposite sides of the pillar, respectively, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar;

first and second field plates respectively disposed in the first and second dielectric regions, the first and second field plates being fully insulated from the extended drain region, the first field plate being laterally surrounded by the pillar, and the second field plate laterally surrounding the pillar;

the sections being arranged in rows and columns substantially across the semiconductor die, adjacent sections in a row or a column being oriented such that the length of the transistor segments in a first one of the adjacent sections extends in a first direction, and the length of the transistor segments in a second one of the adjacent sections extends in a second direction, the first direction being substantially orthogonal to the second direction.

2. The transistor of claim 1 wherein each section is substantially square.

3. The transistor of claim 1 wherein the length is at least 20 times greater than the width.

4. The transistor of claim 1 further comprising a trench gate structure that includes first and second gate members respectively disposed in the first and second dielectric regions near a top of the pillar adjacent the body region.

5. The transistor of claim 1 wherein a ratio of the length to the width of the transistor segments in the first and second sections is in a range of about 30 to 80.

6. The transistor of claim 1 wherein the pillar extends in the first and second lateral directions to form a racetrack-shaped ring or oval.

7. The transistor of claim 1 wherein the plurality of sections comprise 2N sections, where N is an integer greater than or equal to one.

8. A high-voltage, field-effect transistor (HVFET) comprising:

a plurality of transistor segments organized on a die into a plurality of sections, each transistor segment having a length elongated in a first lateral direction and a width in a second lateral direction, the transistor segments of each section being arranged in a side-by-side relationship along the width, each transistor segment including;

a pillar of a semiconductor material of a first conductivity type, the pillar having a racetrack-shape in the first and second lateral directions, the pillar including a source region disposed near a top surface of the die, and an extended drain region that extends in a vertical direction through the die;

first and second dielectric regions disposed on opposite sides of the pillar, respectively, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar;

first and second field plates respectively disposed in the first and second dielectric regions, the first and second field plates being fully insulated from the extended drain region, the first field plate being laterally surrounded by the pillar, and the second field plate laterally surrounding the pillar;

the sections being arranged in rows and columns substantially across the semiconductor die, adjacent sections in a row or a column being oriented such that the length of the transistor segments in a first one of the adjacent sections extends in a first direction, and the length of the transistor segments in a second one of the adjacent sections extends in a second direction, the first direction being substantially orthogonal to the second direction.

9. The HVFET of claim 8 wherein each section is substantially square.

10. The HVFET of claim 8 wherein the length in the first direction is substantially greater than the width in the second direction.

11. The HVFET of claim 10 wherein the length is at least 20 times greater than the width.

12. The HVFET of claim 8 wherein the first and second field plates function as capacitive plates that deplete the extended drain region of charge when the HVFET is in an off-state.

13. The HVFET of claim 8 wherein the plurality of sections comprise 2N sections, where N is an integer greater than or equal to one.