Nonvolatile semiconductor memory device

• US 8,022,460 B2
• Filed: 03/20/2007
• Issued: 09/20/2011
• Est. Priority Date: 03/31/2006
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Takano, Tamae, Furuno, Makoto, Yamazaki, Shunpei, Asami, Yoshinobu
• Primary Examiner(s): Smith; Zandra
• Assistant Examiner(s): Patton; Paul E
• Application Number:
  US11/725,487
• Publication Number:
  US 20070228453A1
• Time in Patent Office: 1,645 Days
• Field of Search: 257/314, 257/315, 257/E21.209, 257/E21.422, 257/E29.304
• US Class Current: 257/314
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/49 comprising different types of peripheral transistor
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An object is to provide a nonvolatile semiconductor memory device which is superior in writing property and charge holding property. A semiconductor substrate in which a channel formation region is formed between a pair of impurity regions is provided, and a first insulating layer, a floating gate electrode, a second insulating layer, and a control gate electrode are provided over the semiconductor substrate. The floating gate electrode includes at least two layers. It is preferable that a band gap of a first floating gate electrode, which is in contact with the first insulating layer, be smaller than that of the semiconductor substrate. It is also preferable that a second floating gate electrode be formed of a metal material, an alloy material, or a metal compound material. This is because, by lowering the bottom energy level of a conduction band of the floating gate electrode than that of the channel formation region in the semiconductor substrate, a carrier injecting property and a charge holding property can be improved.

Claims

1. A nonvolatile semiconductor memory device comprising:

a semiconductor substrate, the semiconductor substrate comprising a pair of impurity regions and a channel formation region between the pair of impurity regions;

a pair of field oxide films embedded in the semiconductor substrate, the pair of impurity regions and the channel formation region being between the pair of field oxide films;

a floating gate electrode over the channel formation region with a first insulating layer interposed therebetween, and

a control gate electrode over the floating gate electrode with a second insulating layer interposed therebetween,

wherein the control gate electrode is across an edge of the floating gate electrode,

wherein a portion of the control gate electrode outside the edge of the floating gate electrode is overlapped with one of the pair of impurity regions,

wherein the first insulating layer is interposed between the portion and the one of the pair of impurity regions and extended to overlap with one of the pair of field oxide films,

wherein the floating gate electrode includes at least a first layer in contact with the first insulating layer, and a second layer over the first layer,

wherein the first layer is formed of a semiconductor material,

wherein a band gap of the first layer is smaller than a band gap of the channel formation region, and

wherein the second layer is formed of a material selected from the group consisting of a metal, a metal alloy, and a metal compound.

5. The nonvolatile semiconductor memory device according to claim 1, wherein there is a difference of 0.1 eV or more between the band gap of the channel formation region and the band gap of the first layer.

6. The nonvolatile semiconductor memory device according to claim 1, wherein the first insulating layer includes a silicon oxide layer and a silicon oxynitride layer formed over the silicon oxide layer.

7. The nonvolatile semiconductor memory device according to claim 6, wherein the floating gate electrode is in contact with the silicon oxynitride layer.

8. The nonvolatile semiconductor memory device according to claim 6, wherein the silicon oxide layer is formed by oxidizing the semiconductor substrate by plasma treatment, and the silicon oxynitride layer is formed by nitriding the silicon oxide layer by plasma treatment.

9. The nonvolatile semiconductor memory device according to claim 1, wherein the second layer includes at least one of tungsten, tantalum, titanium, molybdenum, chromium, and nickel.

10. The nonvolatile semiconductor memory device according to claim 1, wherein the second layer includes at least one of a tantalum nitride, a tungsten nitride, a molybdenum nitride, a titanium nitride, a tantalum oxide, a titanium oxide, and a molybdenum oxide.

29. The nonvolatile semiconductor memory device according to claim 1, wherein the portion of the control gate electrode outside the edge of the floating gate electrode is overlapped with the one of the pair of impurity regions with the first insulating layer and the second insulating layer interposed therebetween.

2. A nonvolatile semiconductor memory device comprising:

a semiconductor substrate, the semiconductor substrate comprising a pair of impurity regions and a channel formation region between the pair of impurity regions;

a pair of field oxide films embedded in the semiconductor substrate, the pair of impurity regions and the channel formation region being between the pair of field oxide films;

a floating gate electrode over the channel formation region with a first insulating layer therebetween, and

a control gate electrode over the floating gate electrode with a second insulating layer interposed therebetween,

wherein the control gate electrode is across an edge of the floating gate electrode,

wherein a portion of the control gate electrode outside the edge of the floating gate electrode is overlapped with one of the pair of impurity regions,

wherein the first insulating layer is interposed between the portion and the one of the pair of impurity regions and extended to overlap with one of the pair of field oxide films,

wherein the floating gate electrode includes at least a first layer and a second layer,

wherein the first layer is in contact with the first insulating layer and is formed using a material having a smaller band gap and lower resistivity than the channel formation region, and

wherein the second layer is formed of a material selected from the group consisting of a metal, a metal alloy, and a metal compound.

11. The nonvolatile semiconductor memory device according to claim 2, wherein there is a difference of 0.1 eV or more between the band gap of the channel formation region and the band gap of the material of the first layer.

12. The nonvolatile semiconductor memory device according to claim 2, wherein the first insulating layer includes a silicon oxide layer and a silicon oxynitride layer formed over the silicon oxide layer.

13. The nonvolatile semiconductor memory device according to claim 12, wherein the floating gate electrode is in contact with the silicon oxynitride layer.

14. The nonvolatile semiconductor memory device according to claim 12, wherein the silicon oxide layer is formed by oxidizing the semiconductor substrate by plasma treatment, and the silicon oxynitride layer is formed by nitriding the silicon oxide layer by plasma treatment.

15. The nonvolatile semiconductor memory device according to claim 2, wherein the second layer includes at least one of tungsten, tantalum, titanium, molybdenum, chromium, and nickel.

16. The nonvolatile semiconductor memory device according to claim 2, wherein the second layer includes at least one of a tantalum nitride, a tungsten nitride, a molybdenum nitride, a titanium nitride, a tantalum oxide, a titanium oxide, and a molybdenum oxide.

30. The nonvolatile semiconductor memory device according to claim 2, wherein the portion of the control gate electrode outside the edge of the floating gate electrode is overlapped with the one of the pair of impurity regions with the first insulating layer and the second insulating layer interposed therebetween.

3. A nonvolatile semiconductor memory device comprising:

a semiconductor substrate, the semiconductor substrate comprising a pair of impurity regions and a channel formation region between the pair of impurity regions;

a pair of field oxide films embedded in the semiconductor substrate, the pair of impurity regions and the channel formation region being between the pair of field oxide films;

a floating gate electrode over the channel formation region with a first insulating layer therebetween, and

a control gate electrode over the floating gate electrode with a second insulating layer interposed therebetween,

wherein the control gate electrode is across an edge of the floating gate electrode,

wherein a portion of the control gate electrode outside the edge of the floating gate electrode is overlapped with one of the pair of impurity regions,

wherein the first insulating layer is interposed between the portion and the one of the pair of impurity regions and extended to overlap with one of the pair of field oxide films,

wherein the floating gate electrode includes at least a first layer and a second layer, and

wherein barrier energy with respect to electrons in the first layer, formed by the first insulating layer, is higher than barrier energy with respect to electrons in the channel formation region, formed by the first insulating layer, and

wherein the second layer is formed of a material selected from the group consisting of a metal, a metal alloy, and a metal compound.

17. The nonvolatile semiconductor memory device according to claim 3, wherein the first insulating layer includes a silicon oxide layer and a silicon oxynitride layer formed over the silicon oxide layer.

18. The nonvolatile semiconductor memory device according to claim 17, wherein the floating gate electrode is in contact with the silicon oxynitride layer.

19. The nonvolatile semiconductor memory device according to claim 17, wherein the silicon oxide layer is formed by oxidizing the semiconductor substrate by plasma treatment, and the silicon oxynitride layer is formed by nitriding the silicon oxide layer by plasma treatment.

20. The nonvolatile semiconductor memory device according to claim 3, wherein the second layer includes at least one of tungsten, tantalum, titanium, molybdenum, chromium, and nickel.

21. The nonvolatile semiconductor memory device according to claim 3, wherein the second layer includes at least one of a tantalum nitride, a tungsten nitride, a molybdenum nitride, a titanium nitride, a tantalum oxide, a titanium oxide, and a molybdenum oxide.

31. The nonvolatile semiconductor memory device according to claim 3, wherein the portion of the control gate electrode outside the edge of the floating gate electrode is overlapped with the one of the pair of impurity regions with the first insulating layer and the second insulating layer interposed therebetween.

4. A nonvolatile semiconductor memory device comprising:

a semiconductor substrate, the semiconductor substrate comprising a pair of impurity regions and a channel formation region between the pair of impurity regions;

a pair of field oxide films embedded in the semiconductor substrate, the pair of impurity regions and the channel formation region being between the pair of field oxide films;

a floating gate electrode over the channel formation region with a first insulating layer therebetween, and

a control gate electrode over the floating gate electrode with a second insulating layer interposed therebetween,

wherein the control gate electrode is across an edge of the floating gate electrode,

wherein a portion of the control gate electrode outside the edge of the floating gate electrode is overlapped with one of the pair of impurity regions,

wherein the first insulating layer is interposed between the portion and the one of the pair of impurity regions and extended to overlap with one of the pair of field oxide films,

wherein the floating gate electrode includes at least a first layer and a second layer,

wherein the first layer which is in contact with the first insulating layer is formed of germanium or a germanium compound, and

wherein the second layer is formed of a material selected from the group consisting of a metal, a metal alloy, and a metal compound.

22. The nonvolatile semiconductor memory device according to claim 4, wherein the first insulating layer includes a silicon oxide layer and a silicon oxynitride layer formed over the silicon oxide layer.

23. The nonvolatile semiconductor memory device according to claim 22, wherein the floating gate electrode is in contact with the silicon oxynitride layer.

24. The nonvolatile semiconductor memory device according to claim 22, wherein the silicon oxide layer is formed by oxidizing the semiconductor substrate by plasma treatment, and the silicon oxynitride layer is formed by nitriding the silicon oxide layer by plasma treatment.

25. The nonvolatile semiconductor memory device according to claim 4, wherein the second layer includes at least one of tungsten, tantalum, titanium, molybdenum, chromium, and nickel.

26. The nonvolatile semiconductor memory device according to claim 4, wherein the second layer includes at least one of a tantalum nitride, a tungsten nitride, a molybdenum nitride, a titanium nitride, a tantalum oxide, a titanium oxide, and a molybdenum oxide.

27. The nonvolatile semiconductor memory device according to claim 4, wherein the first layer has a thickness of 1 nm to 20 nm inclusive.

28. The nonvolatile semiconductor memory device according to claim 4, wherein the germanium compound is a germanium oxide or a germanium nitride.

32. The nonvolatile semiconductor memory device according to claim 4, wherein the portion of the control gate electrode outside the edge of the floating gate electrode is overlapped with the one of the pair of impurity regions with the first insulating layer and the second insulating layer interposed therebetween.