Device configuration of asymmetrical DMOSFET with schottky barrier source

• US 8,022,482 B2
• Filed: 02/14/2006
• Issued: 09/20/2011
• Est. Priority Date: 02/14/2006
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Tai, Sung-Shan, Hu, Yongzhong
• Primary Examiner(s): Cao; Phat
• Assistant Examiner(s): Vieira; Diana C
• Application Number:
  US11/355,128
• Publication Number:
  US 20070187751A1
• Time in Patent Office: 2,044 Days
• Field of Search: 438/92, 257/475, 257/486, 257/328, 257/382, 257/383, 257/384, 257/385, 257/401, 257/485, 257/E29.148, 257/E29.145, 257/288, 257/365, 257/368, 257/754, 257/757, 257/768, 257/769, 257/770, 257/355, 257/356, 257/242, 257/263, 257/302, 257/E27.096, 257/E27.118, 257/E29.626, 257/E29.256, 257/E29.257, 257/E29.263, 257/E29.318
• US Class Current: 257/384
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66507 providing different silicide thicknesses on the gate and on source or drain
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7839 with Schottky drain or source contact
• CPC Class Codes: H01L 29/7845 the means being a conductive material, e.g. silicided S/D or Gate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/1082 Other

Abstract

A trenched semiconductor power device includes a trenched gate insulated by a gate insulation layer and surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a semiconductor substrate. The source region surrounding the trenched gate includes a metal of low barrier height to function as a Schottky source. The metal of low barrier height further may include a PtSi or ErSi layer. In a preferred embodiment, the metal of low barrier height further includes an ErSi layer. The metal of low barrier height further may be a metal silicide layer having the low barrier height. A top oxide layer is disposed under a silicon nitride spacer on top of the trenched gate for insulating the trenched gate from the source region. A source contact disposed in a trench opened into the body region for contacting a body-contact dopant region and covering with a conductive metal layer such as a Ti/TiN layer. In a preferred embodiment, the semiconductor power device constitutes an asymmetrical double diffusion metal oxide semiconductor field effect transistor (DMOSFET) device.

Claims

1. A trenched semiconductor power device comprising a plurality of trenched gates insulated by a gate insulation layer and surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a semiconductor substrate, further comprising:

a source-body contact trench disposed substantially in a middle portion between two of said trenched gates;

each of said trenched gates is covered on top by a spacer cap with vertical cap edges substantially aligned with gate sidewalls of said trenched gates, and said source region surrounding said trenched gates comprising a metal silicide layer extends between said sidewalls of said trenched gates and a sidewall of a the source-body contact trench; and

a low resistance metal layer covering a top surface of said source region comprising said metal silicide layer and also covering the sidewalls and a bottom surface of said source-body contact trench and wherein said source body contact trench is filled with a source contact metal layer directly contacting said low-resistance metal layer whereby said source region comprising said silicide layer contacts said low resistance metal layer on the top surface and on the sidewalls of said source body contact trench.

2. The trenched semiconductor power device of claim 1 wherein:

said source region comprising said metal silicide layer further comprising a PtSi silicide layer.

3. The trenched semiconductor power device of claim 1 wherein:

said source region comprising said metal silicide layer further comprising a ErSi silicide layer.

4. The trenched semiconductor power device of claim 1 wherein:

said source region comprising said metal silicide layer further comprising a metal silicide layer having a thermal stability substantially in a same range as a thermal stability of PtSi silicide and ErSi silicide.

5. The trenched semiconductor power device of claim 1 further comprising:

a top gate insulation layer disposed on top of said trenched gate underneath said spacer cap formed as a concave-shaped insulation spacer for insulating said trenched gate from said source region.

6. The trenched semiconductor power device of claim 1 further comprising:

a top oxide layer disposed on top of said trenched gate underneath said spacer cap formed as a concave-shaped silicon-nitride spacer for insulating said trenched gate from said source region.

7. The trenched semiconductor power device of claim 1 wherein:

said trenched gate is filled with a gate polysilicon up to a level lower than a top surface of a trench of said trenched gate with a top oxide layer filling a top portion of said trenched gate on top of said gate polysilicon with said top oxide layer totally covering said gate polysilicon.

8. The trenched semiconductor power device of claim 1 further comprising:

said low resistance metal layer further comprises a Ti/TiN metal layer covering over the top surface of said source region comprising said metal silicide layer and the sidewalls and the bottom surface of the source-body contact trench.

9. The trenched semiconductor power device of claim 1 wherein:

said semiconductor power device further comprising a N-channel double diffusion metal oxide semiconductor (DMOS) device.

10. The trenched semiconductor power device of claim 1 wherein:

said semiconductor power device further comprising a P-channel DMOS device.

11. The trenched semiconductor power device of claim 1 wherein:

said semiconductor power device further comprising a double diffusion metal oxide semiconductor field effect transistor (DMOSFET) device wherein said source region comprising said metal silicide layer aligned substantially with one of said vertical cap edges of said spacer cap covering on top over said trenched gate; and

said drain region comprising a doped semiconductor region disposed at said bottom surface of said semiconductor substrate opposite vertically from said source region.

12. The trenched semiconductor power device of claim 2 further comprising:

a top gate insulation layer disposed on top of said trenched gate underneath said spacer cap formed as a concave-shaped insulation spacer extends laterally over substantially an entire top surface of the trenched gate for insulating said trenched gate from said source region; and

an insulation layer formed on top of said trenched spacer cap and said source region to further insulate the trenched gate from the source contact metal layer.

13. The trenched semiconductor power device of claim 1 further comprising:

a top gate insulation layer disposed on top of said trenched gate underneath said spacer cap formed as a self-aligned concave-shaped insulation spacer extends laterally over the top gate insulation layer on top of the trenched gate to totally covering said top gate insulation layer for insulating said trenched gate from said source region.