Increasing body dopant uniformity in multi-gate transistor devices

• US 8,022,487 B2
• Filed: 04/29/2008
• Issued: 09/20/2011
• Est. Priority Date: 04/29/2008
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kavalieros, Jack T., Dewey, Gilbert, Rakshit, Titash, Pillarisetty, Ravi, Rachmady, Willy
• Primary Examiner(s): MENZ, LAURA MARY
• Application Number:
  US12/111,714
• Publication Number:
  US 20090267161A1
• Time in Patent Office: 1,239 Days
• Field of Search: 257/402, 257/190, 257/192
• US Class Current: 257/402
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Techniques and structures for increasing body dopant uniformity in multi-gate transistor devices are generally described. In one example, an electronic device includes a semiconductor substrate, a multi-gate fin coupled with the semiconductor substrate, the multi-gate fin comprising a source region, a drain region, and a gate region wherein the gate region is disposed between the source region and the drain region, the gate region being body-doped after a sacrificial gate structure is removed from the multi-gate fin and before a subsequent gate structure is formed, a dielectric material coupled with the source region and the drain region of the multi-gate fin, and the subsequent gate structure coupled to the gate region of the multi-gate fin.

Claims

1. An apparatus comprising:

a semiconductor substrate;

a multi-gate fin coupled with the semiconductor substrate, the multi-gate fin comprising a source region, a drain region, and a gate region wherein the gate region is disposed between the source region and the drain region, the gate region being body-doped after higher temperature operations on the apparatus have been performed and a sacrificial gate structure is removed from the multi-gate fin, and before a subsequent gate structure is formed;

a dielectric material coupled with the source region and the drain region of the multi-gate fin; and

the subsequent gate structure coupled to the gate region of the multi-gate fin.

2. An apparatus according to claim 1, wherein the gate region of the multi-gate fin is body-doped after the sacrificial gate structure is removed to increase body dopant uniformity in the multi-gate fin by avoiding higher temperature operations that increase body dopant segregation, the higher temperature operations comprise temperatures greater than about 700°

C.

3. An apparatus according to claim 1, wherein the multi-gate fin comprises a first surface, a second surface, and a third surface wherein the first surface and the third surface are substantially parallel to one another and wherein the first surface and the second surface are substantially perpendicular to one another, wherein the gate region of the multi-gate fin is body-doped at an angle between about 10 degrees and about 80 degrees relative to the second surface.

4. An apparatus according to claim 3, wherein the first surface, the second surface, and the third surface of the multi-gate fin are body-doped at an angle between about 40 degrees and about 70 degrees relative to the second surface.

5. An apparatus according to claim 1, wherein the body-doped gate region of the multi-gate fin comprises an n-type dopant for a p-type metal-oxide-semiconductor (PMOS) device or wherein the body-doped gate region of the multi-gate fin comprises a p-type dopant for an n-type metal-oxide-semiconductor (NMOS) device.

6. An apparatus according to claim 1, further comprising:

a spacer structure coupled to the multi-gate fin, the spacer structure being disposed between the dielectric material and the subsequent gate structure.

7. An apparatus according to claim 1, wherein the subsequent gate structure comprises:

a subsequent gate dielectric coupled to the gate region of the multi-gate fin; and

a subsequent gate electrode coupled to the gate dielectric.