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Edge connect wafer level stacking

  • US 8,022,527 B2
  • Filed: 10/20/2010
  • Issued: 09/20/2011
  • Est. Priority Date: 10/10/2006
  • Status: Active Grant
First Claim
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1. A stacked microelectronic package comprising:

  • a plurality of subassemblies including a first subassembly and a second subassembly underlying the first subassembly, each subassembly having a front face and a rear face remote from the front face, each of the first and second subassemblies including a plurality of front contacts exposed at the front face, at least one edge and a plurality of front traces extending about the respective at least one edge, the second subassembly having a plurality of rear contacts exposed at the rear face and a plurality of rear traces extending from the rear contacts about the at least one edge to at least some of the plurality of front contacts of at least one of the first or second subassemblies, and a substrate underlying the second subassembly, the substrate having a relief channel aligned with the at least one edge of each subassembly.

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