Top layers of metal for high performance IC's

• US 8,022,546 B2
• Filed: 06/13/2008
• Issued: 09/20/2011
• Est. Priority Date: 12/21/1998
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan
• Primary Examiner(s): PIZARRO CRESPO, MARCOS D
• Application Number:
  US12/138,453
• Publication Number:
  US 20080246154A1
• Time in Patent Office: 1,194 Days
• Field of Search: 257/690, 257/700, 257/750, 257758-760, 257/780, 257/781, 257/784, 257/E23.019, 257/E23.142
• US Class Current: 257/758
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/1148 Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 : Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 23/53295 : Stacked insulating layers
• CPC Class Codes: H01L 23/60 : Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 27/0676 : comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/08 : including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15184 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads for flip chip applications. Photoresist defined electroplating, sputter/etch, or dual and triple damascene techniques are used for forming the metal lines and via fill.

Claims

1. A semiconductor chip comprising:

a silicon substrate;

a transistor in or on said silicon substrate;

a metallization structure over said silicon substrate, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a dielectric layer between said first and second metal layers;

a passivation layer over said metallization structure and over said dielectric layer, wherein a first opening in said passivation layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of said first opening, wherein said passivation layer comprises a nitride;

a first polymer layer on said passivation layer, wherein a second opening in said first polymer layer is over said first contact point, wherein said first polymer layer has a thickness between 2 and 50 micrometers;

a third metal layer on said first polymer layer and on said first contact point, wherein said third metal layer comprises a titanium-containing layer with a thickness between 0.01 and 3 micrometers on said first polymer layer and on said first contact point, a gold seed layer with a thickness between 0.05 and 3 micrometers on said titanium-containing layer, and an electroplated gold layer with a thickness between 2 and 100 micrometers on said gold seed layer; and

a second polymer layer on said third metal layer and on said first polymer layer.

2. The semiconductor chip of claim 1, wherein said titanium-containing layer comprises a titanium-tungsten-alloy layer on said first polymer layer and on said first contact point.

3. The semiconductor chip of claim 1, wherein said titanium-containing layer comprises a titanium-nitride layer on said first polymer layer and on said first contact point.

4. The semiconductor chip of claim 1, wherein said first polymer layer comprises polyimide.

5. The semiconductor chip of claim 1, wherein said first polymer layer comprises benzocyclobutene (BCB).

6. The semiconductor chip of claim 1, wherein a third opening in said second polymer layer is over a second contact point said third metal layer, and said second contact point is at a bottom of said third opening, wherein said second contact point is connected to said first contact point through said third metal layer.

7. The semiconductor chip of claim 1, wherein said passivation layer further comprises an oxide.

8. A semiconductor chip comprising:

a silicon substrate;

a transistor in or on said silicon substrate;

a metallization structure over said silicon substrate, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a dielectric layer between said first and second metal layers;

a passivation layer over said metallization structure and over said dielectric layer, wherein a first opening in said passivation layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of said first opening, wherein said passivation layer comprises a nitride;

a third metal layer over said passivation layer and on said first contact point, wherein said third metal layer comprises a titanium-containing layer with a thickness between 0.01 and 3 micrometers over said passivation layer and on said first contact point, a gold seed layer with a thickness between 0.05 and 3 micrometers on said titanium-containing layer, and an electroplated gold layer with a thickness between 2 and 100 micrometers on said gold seed layer; and

a polymer layer on said third metal layer and over said passivation layer.

9. The semiconductor chip of claim 8, wherein said titanium-containing layer comprises a titanium-tungsten-alloy layer over said passivation layer and on said first contact point.

10. The semiconductor chip of claim 8, wherein said titanium-containing layer comprises a titanium-nitride layer over said passivation layer and on said first contact point.

11. The semiconductor chip of claim 8, wherein a second opening in said polymer layer is over a second contact point of said third metal layer, and said second contact point is at a bottom of said second opening, wherein said second contact point is connected to said first contact point through said third metal layer.

12. The semiconductor chip of claim 8, wherein said passivation layer further comprises an oxide.

13. A semiconductor chip comprising:

a silicon substrate;

a transistor in or on said silicon substrate;

a metallization structure over said silicon substrate, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a dielectric layer between said first and second metal layers;

a passivation layer over said metallization structure and over said dielectric layer, wherein a first opening in said passivation layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of said first opening, wherein said passivation layer comprises a nitride;

a polymer layer on said passivation layer, wherein said polymer layer has a thickness between 2 and 50 micrometers; and

a third metal layer on said polymer layer and on said first contact point, wherein said third metal layer comprises a copper seed layer with a thickness between 0.05 and 3 micrometers over said polymer layer and over said first contact point, an electroplated copper layer with a thickness between 2 and 100 micrometers on said copper seed layer, and a nickel-containing layer over said electroplated copper layer, wherein said third metal layer is configured for wirebonding.

14. The semiconductor chip of claim 13, wherein said third metal layer further comprises a titanium-containing layer under said copper seed layer, on said first contact point and on said polymer layer, wherein said titanium-containing layer has a thickness between 0.01 and 3 micrometers.

15. The semiconductor chip of claim 13, wherein said third metal layer further comprises a titanium-nitride layer under said copper seed layer, on said first contact point and on said polymer layer, wherein said titanium-nitride layer has a thickness between 0.01 and 3 micrometers.

16. The semiconductor chip of claim 13, wherein said third metal layer further comprises a chromium-containing layer under said copper seed layer, on said first contact point and on said polymer layer, wherein said chromium-containing layer has a thickness between 0.01 and 3 micrometers.

17. The semiconductor chip of claim 13, wherein said passivation layer further comprises an oxide.

18. The semiconductor chip of claim 13, wherein said polymer layer comprises polyimide.

19. The semiconductor chip of claim 13, wherein said polymer layer comprises benzocyclobutene (BCB).

20. The semiconductor chip of claim 13, wherein a second opening in said passivation layer is over a second contact point of said metallization structure, and exposes said second contact point is at a bottom of said second opening, wherein said third metal layer is further on said second contact point, wherein said first contact point is connected to said second contact point through said third metal layer.

21. A semiconductor chip comprising:

a silicon substrate;

a transistor in or on said silicon substrate;

a metallization structure over said silicon substrate, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a dielectric layer between said first and second metal layers;

a passivation layer over said metallization structure and over said dielectric layer, wherein a first opening in said passivation layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of said first opening, wherein a second opening in said passivation layer is over a second contact point of said metallization structure, and said second contact point is at a bottom of said second opening, wherein said first opening has a width between 0.5 and 3 micrometers, wherein said passivation layer comprises a nitride; and

a third metal layer on said passivation layer and on said first and second contact points, wherein said first contact point is connected to said second contact point through said third metal layer, wherein there is no polymer layer between said third metal layer and said passivation layer, wherein said third metal layer comprises an adhesion layer, a copper seed layer on said adhesion layer, and an electroplated copper layer with a thickness between 2 and 100 micrometers on said copper seed layer, wherein said third metal layer is configured for wirebonding.

22. The semiconductor chip of claim 21, wherein said passivation layer further comprises an oxide.

23. The semiconductor chip of claim 21, wherein said electroplated copper layer is capped with nickel.

24. The semiconductor chip of claim 21 further comprising a polymer layer on said third metal layer and over said passivation layer.