Advanced repeater with duty cycle adjustment

• US 8,022,731 B2
• Filed: 04/14/2010
• Issued: 09/20/2011
• Est. Priority Date: 06/30/2005
• Status: Expired due to Fees

• Current Assignee: Scott Pitkethly
• Original Assignee: Scott Pitkethly
• Inventors: Pitkethly, Scott
• Primary Examiner(s): Chang; Daniel D
• Application Number:
  US12/760,054
• Publication Number:
  US 20100295577A1
• Time in Patent Office: 524 Days
• Field of Search: 326/83, 326/85, 326/86, 326/87, 326/91, 326/27, 326/29, 327/175, 327/178
• US Class Current: 326/87
• CPC Class Codes: H03K 19/01721 by means of a pull-up or down element
• CPC Class Codes: H03K 5/1565 the output pulses having a constant duty cycle

Abstract

An advanced repeater with duty cycle adjustment. In accordance with a first embodiment of the present invention, an advanced repeater includes an output stage for driving an output signal line responsive to an input signal and a plurality of active devices for selectably adjusting a duty cycle of the signal. The advanced repeater may further include circuitry for producing a delayed version of the signal.

Claims

1. A circuit, comprising:

means for adjusting a duty cycle of an output signal that is associated with an input signal; and

means for driving an output level that corresponds to a transition of said input signal, wherein said driving is terminated prior to a subsequent transition of said input signal.

2. The circuit of claim 1 further comprising means for producing a delayed version of said input signal.

3. The circuit of claim 1 further comprising:

means for receiving said input signal; and

means for outputting said output signal, wherein a delayed version of said input signal is coupled to said means for receiving said input signal.

4. The circuit of claim 3 wherein a first drive level and a second drive level are used to drive an output terminal of said means for outputting said output signal wherein said second drive level is substantially weaker than said first drive level.

5. The circuit of claim 3 wherein said delayed version of said input signal is used to change a drive level of an output terminal of said means for outputting said output signal.

6. A circuit, comprising:

receiving circuitry configured to receive an input signal;

duty cycle adjusting circuitry configured to adjust a duty cycle of an output signal that is associated with said input signal;

driving circuitry configured to drive an output level that corresponds to a transition of said input signal, wherein said driving is terminated prior to a subsequent transition of said input signal; and

output circuitry configured to output said output signal.

7. The circuit of claim 6 wherein a delayed version of said output signal is coupled to said receiving circuitry.

8. The circuit of claim 6 wherein a delayed version of said input signal is coupled to said receiving circuitry.

9. The circuit of claim 6 wherein a first drive level and a second drive level are used to drive an output terminal of said output circuitry wherein said second drive level is substantially weaker than said first drive level.

10. The circuit of claim 6 wherein a delayed version of one of said input signal and said output signal is used to change a drive level of an output signal line.

11. A circuit, comprising:

duty cycle adjusting circuitry for adjusting a duty cycle of an output signal; and

output level driving circuitry coupled to said duty cycle adjusting circuitry for driving an output level that corresponds to a first transition of an input signal, wherein said driving is terminated prior to a second transition of said input signal subsequent to said first transition.

12. The circuit of claim 11 further comprising circuitry configured to produce a delayed version of said input signal.

13. The circuit of claim 11 further comprising circuitry configured to produce a delayed version of said output signal.

14. The circuit of claim 11 further comprising:

circuitry configured to receive said input signal; and

circuitry configured to output said output signal, wherein a delayed version of said input signal is coupled to an input of said circuitry configured to receive said input signal.

15. The circuit of claim 11 wherein said output signal is inverted relative to said input signal.

16. The circuit of claim 12 wherein said circuitry configured to produce a delayed version of said input signal comprises no discrete components.

17. A method, comprising:

driving an output signal line, responsive to an input signal, to generate an output signal;

selectably adjusting a duty cycle of said output wherein a drive configuration is selected to determine a drive level of said output signal line; and

producing a delayed version of said input signal wherein said delay is greater than a transition time associated with said driving said output signal line less a delay associated with said selectably adjusting said duty cycle.

18. The method of claim 17 wherein said output signal line is inverted relative to said signal.

19. The method of claim 17 wherein a first drive level and a second drive level are used to drive said output signal line and said second drive level is substantially weaker than said first drive level.

20. The method of claim 17 wherein said delayed version of said input signal is used to change a drive level of said output signal line.