Demodulation circuit

• US 8,022,754 B2
• Filed: 06/10/2009
• Issued: 09/20/2011
• Est. Priority Date: 03/14/2007
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Radecki, Andrzej, Yamazaki, Daisuke
• Primary Examiner(s): Chang; Joseph
• Application Number:
  US12/482,224
• Publication Number:
  US 20090243716A1
• Time in Patent Office: 832 Days
• Field of Search: 329/369, 329/370
• US Class Current: 329/369
• CPC Class Codes: H03D 1/10 of diodes
• CPC Class Codes: H03D 1/18 of semiconductor devices
• CPC Class Codes: H04L 27/06 Demodulator circuits; Receiver circuits

Abstract

A demodulation circuit, including: an input terminal (IN) inputting a current amplitude modulated signal; a first transistor (101) connected to the input terminal; a capacitance (105) connected to a control terminal of the first transistor; a diode (102) connected between the input terminal and the control terminal of the first transistor; and a first current source (104) applying a current of the input terminal, is provided.

Claims

1. A demodulation circuit, comprising:

an input terminal inputting a current amplitude modulated signal;

a first transistor connected to said input terminal;

a capacitance connected to a control terminal of said first transistor;

a diode connected between said input terminal and the control terminal of said first transistor;

a first current source applying a current of said input terminal; and

a first comparator comparing a voltage of said input terminal and a voltage of the control terminal of said first transistor.

2. The demodulation circuit according to claim 1, further comprising:

a switch interrupting the current flowing in said first current source in accordance with a comparison result of said first comparator.

4. The demodulation circuit according to claim 1, wherein said first current source is connected to the control terminal of said first transistor.

6. The demodulation circuit according to claim 1, further comprising:

an abnormality detector lowering the voltage of the control terminal of said first transistor when a time when the voltage of said input terminal is lower than the voltage of the control terminal of said first transistor is longer than a threshold value.

7. The demodulation circuit according to claim 6, wherein said abnormality detector includes:

a timer outputting a voltage in accordance with the time when the voltage of said input terminal is lower than the voltage of the control terminal of said first transistor;

a second comparator comparing the voltage outputted from the timer and a threshold value; and

a switch connecting the control terminal of said first transistor to a reference potential in accordance with a comparison result of the second comparator.

8. The demodulation circuit according to claim 1, further comprising:

a second current source connected to the control terminal of said first transistor,

wherein said first current source is connected to said input terminal.

9. The demodulation circuit according to claim 8, wherein a size of the current in said first current source is controlled in accordance with the voltage of the control terminal of said first transistor.

10. The demodulation circuit according to claim 8, wherein said first current source is constituted by a field-effect transistor of which gate is connected to the control terminal of said first transistor and drain is connected to said input terminal.

11. The demodulation circuit according to claim 10, wherein a drain of the field-effect transistor is connected to said input terminal via a load.

12. The demodulation circuit according to claim 1, wherein said diode is constituted by a field-effect transistor of which gate and drain are mutually connected.

13. The demodulation circuit according to claim 12, wherein said first current source is constituted by a field-effect transistor of which gate and drain are connected to the control terminal of said first transistor.

14. The demodulation circuit according to claim 13, further comprising:

a first switch interrupting the current flowing in said first current source in accordance with a comparison result of said first comparator.

15. The demodulation circuit according to claim 14, further comprising:

an abnormality detector lowering the voltage of the control terminal of said first transistor when a time when the voltage of said input terminal is lower than the voltage of the control terminal of said first transistor is longer than a threshold value.

16. The demodulation circuit according to claim 15, wherein said abnormality detector includes:

a timer outputting a voltage in accordance with the time when the voltage of said input terminal is lower than the voltage of the control terminal of said first transistor;

a second comparator comparing the voltage outputted from the timer and a threshold value; and

a second switch connecting the control terminal of said first transistor to a reference potential in accordance with a comparison result of the second comparator.

17. The demodulation circuit according to claim 1, further comprising:

a second current source connected to the control terminal of said first transistor,

wherein said first current source is connected to said input terminal.

18. The demodulation circuit according to claim 17, wherein said first current source is constituted by a field-effect transistor of which gate is connected to the control terminal of said first transistor, and drain is connected to said input terminal.

19. The demodulation circuit according to claim 18, wherein a drain of the field-effect transistor is connected to said input terminal via a load.

3. A demodulation circuit, comprising:

an input terminal inputting a current amplitude modulated signal;

a first transistor connected to said input terminal;

a capacitance connected to a control terminal of said first transistor;

a diode connected between said input terminal and the control terminal of said first transistor; and

a first current source applying a current of said input terminal,

wherein said diode is constituted by a field-effect transistor of which gate and drain are mutually connected.

5. A demodulation circuit, comprising:

an input terminal inputting a current amplitude modulated signal;

a first transistor connected to said input terminal;

a capacitance connected to a control terminal of said first transistor;

a diode connected between said input terminal and the control terminal of said first transistor; and

a first current source applying a current of said input terminal,

wherein said first current source is connected to the control terminal of said first transistor and includes a field-effect transistor of which gate and drain are connected to the control terminal of said first transistor.