Pixel sensor with voltage compensator

• US 8,023,020 B2
• Filed: 07/12/2010
• Issued: 09/20/2011
• Est. Priority Date: 02/17/2003
• Status: Expired due to Fees

• Current Assignee: Silverbrook Research Pty Limited
• Original Assignee: Silverbrook Research Pty Limited
• Inventors: Ridley, Nicholas Damon, Silverbrook, Kia, Moini, Alireza, Yourlo, Zhenya Alexander, Lapstun, Paul, Underwood, Matthew John, Henderson, Peter Charles Boyd
• Primary Examiner(s): Chan; Jason
• Assistant Examiner(s): PRABHAKHER, PRITHAM DAVID
• Application Number:
  US12/834,888
• Publication Number:
  US 20100302426A1
• Time in Patent Office: 435 Days
• Field of Search: 348294-310
• US Class Current: 348/294
• CPC Class Codes: H04N 25/59 by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array

Abstract

A photodetecting circuit is disclosed. The photodetecting circuit includes a photodetector, a storage node with first and second node terminals, a transfer transistor disposed intermediate the first node terminal of the storage node and the photodetector for electrically connecting the first node terminal and the photodetector upon receiving a transfer signal to a gate of the transfer transistor, a reset transistor disposed intermediate a reset voltage node and the first node terminal of the storage node for electrically connecting the first node terminal to the reset voltage node upon receiving a reset signal to a gate of the reset transistor, and an output circuit for generating an output signal based on a voltage at the first terminal. First the reset signal is applied, followed by the transfer signal. Next, a compensation signal is applied at the second terminal of the storage node. The compensation signal increases the voltage at the first terminal whilst the output circuit generates the output signal. The compensation signal is a logically negated version of the transfer signal.

Claims

1. A photodetecting circuit comprising:

a photodetector;

a storage node having first and second node terminals;

a transfer transistor, disposed intermediate the first node terminal of the storage node and the photodetector, for electrically connecting the first node terminal and the photodetector upon receiving a transfer signal to a gate of the transfer transistor;

a reset transistor, disposed intermediate a reset voltage node and the first node terminal of the storage node, for electrically connecting the first node terminal to the reset voltage node upon receiving a reset signal to a gate of the reset transistor; and

an output circuit for generating an output signal based on a voltage at the first terminal;

the photodetecting circuit being configured to;

receive the reset signal;

receive the transfer signal; and

receive a compensation signal at the second terminal of the storage node, the compensation signal increasing the voltage at the first terminal whilst the output circuit generates the output signal, the compensation signal being a logically negated version of the transfer signal.

2. A photodetecting circuit according to claim 1, wherein the storage node includes a capacitor.

3. A photodetecting circuit according to claim 1, wherein the output circuit includes an output transistor, a current through which is controlled by the voltage at the first node terminal.

4. A photodetector circuit according to claim 1, the photodetector circuit being a CMOS circuit.

5. A monolithic integrated circuit including:

a plurality of photodetector circuits according to claim 1;

at least one analog to digital converter for converting output signals generated by respective photodetector circuits into digital image data; and

a framestore for storing frames of the digital image data.