Dynamic memory word line driver scheme

• US 8,023,314 B2
• Filed: 03/16/2009
• Issued: 09/20/2011
• Est. Priority Date: 04/06/1990
• Status: Expired due to Fees

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Lines, Valerie L.
• Primary Examiner(s): Luu; Pho M
• Application Number:
  US12/405,153
• Publication Number:
  US 20090237981A1
• Time in Patent Office: 918 Days
• Field of Search: 365/149, 365/150, 365/189.18, 365/230.06
• US Class Current: 365/149
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The circuit eliminates the need for a double-boot-strapping circuit, and ensures that no voltages exceed that necessary to fully turn on a memory cell access transistor. Voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained. A DRAM includes word lines, memory cells having enable inputs connected to the word lines, a gate receiving word line selecting signals at first logic levels V_ss and V_dd, and for providing a select signal at levels V_ss and V_dd, a high voltage supply source V_pp which is higher in voltage than V_dd, a circuit for translating the select signals at levels V_ss and V_dd to levels V_ss and V_pp and for applying it directly to the word lines whereby an above V_dd voltage level word line is achieved without the use of double boot-strap circuits.

Claims

1. An apparatus for selecting a word line and writing to memory cells in a dynamic random access memory (DRAM), the apparatus comprising:

a level shifter circuit including at least first and second transistors having their respective sources directly connected to a controlled high supply voltage level Vpp supplied from a high voltage supply, the level shifter circuit being configured to;

respond to a decoded address input signal selectively having logic voltage levels that are less than the controlled voltage level Vpp, the drain of the first transistor being configured to apply current to a first node, the drain of the second transistor being configured to apply current to a second node, the first and second transistors being gated from the second and first nodes, respectively, and

produce a control signal selectively having the controlled high supply voltage level Vpp or a Vss voltage level; and

a driving circuit to drive a selected word line to the controlled high supply voltage level Vpp in response to the control signal to write a logic voltage level in a DRAM cell storage capacitor associated with the selected word line.

2. The apparatus of claim 1 wherein the driver comprises:

a third transistor for coupling the controlled high supply voltage level Vpp and the word line in response to the control signal to drive the selected word line.

3. The apparatus of claim 1 wherein the driver comprises:

a third transistor for coupling a secondary decoder output, having an output voltage level at the controlled high supply voltage level Vpp, and the word line in response to the control signal to drive the selected word line.

4. The apparatus of claim 1 wherein the level shifter circuit further includes:

a fourth transistor and a fifth transistor configured to respond to the decoded address input signal to gate the first and second transistors.

5. The apparatus of claim 4 wherein:

the first and second transistors are P-channel FETs; and

the fourth and fifth transistors are N-channel FETs, the drains of the first and second transistors being pulled down by the fourth and fifth transistors, respectively, in response to the decoded address input signal.

6. The apparatus of claim 1 wherein:

the gate of the first transistor is directly connected to the drain of the second transistor; and

the gate of the second transistor is directly connected to the drain of the first transistor.

7. A dynamic random access memory (DRAM) for storing a voltage level in a memory cell coupled to a word line and a bit line, the DRAM comprising:

a level shifter circuit including at least first and second transistors having their respective sources directly connected to a controlled high supply voltage level Vpp supplied from a high voltage supply, the level shifter circuit being configured to;

respond to a decoded address input signal selectively having logic voltage levels that are less than the controlled voltage level Vpp, the drain of the first transistor being configured to apply current to a first node, the drain of the second transistor being configured to apply current to a second node, the first and second transistors being gated from the second and first nodes, respectively, and

produce a control signal selectively having the controlled high supply voltage level Vpp or a low voltage level; and

a driving circuit to drive a selected word line to the controlled high supply voltage level Vpp in response to the control signal to write a logic voltage level in a DRAM cell storage capacitor associated with the selected word line.

8. The DRAM of claim 7 wherein the driver comprises:

a third transistor for coupling the controlled high supply voltage level Vpp and the word line in response to the control signal to drive the selected word line.

9. The DRAM of claim 7 wherein the driver comprises:

a third transistor for coupling a secondary decoder output, having an output voltage level at the controlled high supply voltage level Vpp, and the word line in response to the control signal to drive the selected word line.

10. The DRAM of claim 7 wherein the level shifter circuit further includes:

a fourth transistor and a fifth transistor configured to respond to the decoded address input signal to gate the first and second transistors.

11. The DRAM of claim 10 wherein:

the first and second transistors are P-channel FETs; and

the fourth and fifth transistors are N-channel FETs, the drains of the first and second transistors being pulled down by the fourth and fifth transistors, respectively, in response to the decoded address input signal.

12. The DRAM of claim 7 wherein:

the gate of the first transistor is directly connected to the drain of the second transistor; and

the gate of the second transistor is directly connected to the drain of the first transistor.

13. A dynamic random access memory (DRAM) comprising a word line driver configured to:

receive a word line select address signal having a selected one of a low logic level voltage Vss and a high logic level voltage Vdd, and

selectively apply a controlled high supply voltage Vpp to the word line through the source-drain circuit of a P-channel pass FET, the controlled high supply voltage Vpp being substantially equal to or greater than the high logic level voltage Vdd plus one FET threshold voltage (Vdd+Vtn),

the controlled high supply voltage Vpp being directly connected to the sources of first and second pull-up FETs,

the gate of the second pull-up FET and the drain of the first pull-up FET being coupled to a first node,

the gate of the first pull-up FET and the drain of the second pull-up FET being coupled to a second node,

the drain of a first pull-down FET being coupled to the first node, the drain of a second pull-down FET being coupled to the second node,

the first and second pull-up FETs being gated from the second and first nodes, respectively, in response to the word line select address signal to provide a control signal selectively having the high supply voltage Vpp or a Vss voltage level to the gate of the P- channel pass FET.

14. The DRAM of claim 13 wherein the word line driver includes:

a third pull-down FET for selectively pulling down the second node in response to the control signal.

15. The DRAM of claim 14 wherein the word line driver further includes:

a logic gate for responding solely to the logic states of the word line select address signals to produce a node driving signal.

16. The DRAM of claim 15 wherein the node driving signal comprises:

first and second driving signals that are provided to the gates of the first and second pull-down FETs, respectively.

17. The DRAM of claim 16 wherein the word line driver further includes:

an inverter for inverting the second driving signal to produce the first driving signal.

18. The DRAM of claim 13 wherein the word line driver includes:

a third pull-down FET for selectively pulling down the word line in response to the control signal being provided to the gate thereof.

19. The DRAM of claim 13, wherein a decoded secondary decoder output provides the controlled high supply voltage Vpp to the source-drain circuit of the P-channel pass FET.

20. The DRAM of claim 13, wherein the controlled high supply voltage Vpp is directly connected to the source-drain circuit of the P-channel pass FET.

21. The DRAM of claim 13 wherein:

the gate of the first transistor is directly connected to the drain of the second transistor; and

the gate of the second transistor is directly connected to the drain of the first transistor.