Non-volatile semiconductor memory device

• US 8,023,327 B2
• Filed: 07/08/2009
• Issued: 09/20/2011
• Est. Priority Date: 09/12/2008
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Futatsuyama, Takuya
• Primary Examiner(s): Nguyen; Tuan
• Assistant Examiner(s): LE, TOAN K
• Application Number:
  US12/499,237
• Publication Number:
  US 20100067299A1
• Time in Patent Office: 804 Days
• Field of Search: 365/185.17, 365/185.2, 365/185.22, 365/185.29
• US Class Current: 365/185.17
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells

Abstract

A memory device including a NAND string with multiple memory cells connected in series, one end of the NAND string being coupled to a bit line via a first select gate transistor while the other end is coupled to a source line via a second select gate transistor, wherein the device has a data read mode performed under the bias condition of: a selected cell is applied with a read voltage; and unselected cells are applied with read pass voltages, and wherein in the data read mode, one of the unselected cells adjacent to one of the first and second select gate transistor is applied with a first read pass voltage while the other unselected cells are applied with a second read pass voltage lower than the first read pass voltage.

Claims

1. A non-volatile semiconductor memory device comprising a NAND string, in which multiple memory cells are connected in series, one end of the NAND string being coupled to a bit line via a first select gate transistor while the other end is coupled to a source line via a second select gate transistor, wherein

the memory device has a data read mode performed under the bias condition of:

a selected cell in the NAND string is applied with a read voltage; and

unselected cells in the NAND string are applied with read pass voltages set to turn on cells without regard to cell data, and wherein

in the data read mode, one of the unselected cells adjacent to one of the first and second select gate transistor is applied with a first read pass voltage, two unselected cells adjacent to the selected cell are applied with the first read pass voltage, and the other unselected cells are applied with a second read pass voltage lower than the first read pass voltage.

2. The non-volatile semiconductor memory device according to claim 1, wherein

the memory device has an erase-verify mode for erase-judging by detecting whether the bit line is charged-up to a certain level or not with cell current carried from the source line to the bit line under the condition that all cells in the NAND string are applied with a voltage equal to or higher than the ground potential;

the second select gate transistor is turned on; and

the first select gate transistor is turned on later than the second select gate transistor, and wherein

in the data read mode, the one of the unselected cells disposed adjacent to the first select gate transistor is applied with the first read pass voltage higher than the second read pass voltage applied to the other unselected cells.

3. The non-volatile semiconductor memory device according to claim 1, wherein

the memory device has an erase-verify mode for erase-judging by detecting whether the bit line is lowered to a certain level or not with cell current carried from the bit line to the source line under the condition that all cells in the NAND string are applied with a voltage equal to or higher than the ground potential;

the source line and a well on which the NAND string is formed are applied with a positive voltage;

the bit line is applied with a bit line voltage higher than the positive voltage;

the first select gate transistor is turned on; and

the second select gate transistor is turned on later than the first select gate transistor, and wherein

in the data read mode, the one of the unselected cells disposed adjacent to the second select gate transistor is applied with the first read pass voltage higher than the second read pass voltage applied to the other unselected cells.

4. The non-volatile semiconductor memory device according to claim 1, wherein

the one of the unselected cells adjacent to one of the first and second select gate transistor, which is applied with the first read pass voltage, is a dummy cell.

5. A non-volatile semiconductor memory device comprising a NAND string, in which multiple memory cells are connected in series, one end of the NAND string being coupled to a bit line via a first select gate transistor while the other end is coupled to a source line via a second select gate transistor, control gates of the memory cells being coupled to word lines respectively while gates of the first and second select gate transistors are coupled to first and second select gate lines, respectively, wherein

the memory device has a data read mode performed under the bias condition of:

a selected word line in the NAND string is applied with a read voltage;

an unselected word line adjacent to one of the first and second select gate lines is applied with a first read pass voltage;

two unselected word lines adjacent to the selected word line are applied with the first read pass voltage; and

the other unselected word lines are applied with a second read pass voltage lower than the first read pass voltage.

6. The non-volatile semiconductor memory device according to claim 5, wherein

the memory device has an erase-verify mode for erase-judging by detecting whether the bit line is charged-up to a certain level or not with cell current carried from the source line to the bit line under the condition that all word lines in the NAND string are set at a voltage equal to or higher than the ground potential;

the second select gate transistor is turned on; and

the first select gate transistor is turned on later than the second select gate transistor, and wherein

in the data read mode, the unselected word line adjacent to the first select gate line is applied with the first read pass voltage higher than the second read pass voltage applied to the other unselected word lines.

7. The non-volatile semiconductor memory device according to claim 5, wherein

the memory device has an erase-verify mode for erase-judging by detecting whether the bit line is lowered to a certain level or not with cell current carried from the bit line to the source line under the condition that all word lines in the NAND string are set at a voltage equal to or higher than the ground potential;

the source line and a well on which the NAND string is formed are applied with a positive voltage;

the bit line is applied with a bit line voltage higher than the positive voltage;

the first select gate transistor is turned on; and

the second select gate transistor is turned on later than the first select gate transistor, and wherein

in the data read mode, the unselected word line adjacent to the second select gate line is applied with the first read pass voltage higher than the second read pass voltage applied to the other unselected word lines.

8. The non-volatile semiconductor memory device according to claim 5, wherein

the unselected word line adjacent to one of the first and second select gate lines applied with the first read pass voltage is a dummy word line.

9. A non-volatile semiconductor memory device comprising a NAND string, in which multiple memory cells are connected in series, one end of the NAND string being coupled to a bit line via a first select gate transistor while the other end is coupled to a source line via a second select gate transistor, first and second dummy cells being inserted in the NAND string to be disposed adjacent to the first and second select gate transistors, respectively, control gates of the memory cells and the first and second dummy cells being coupled to word lines and first and second dummy word lines, respectively, while gates of the first and second select gate transistors are coupled to first and second select gate lines, respectively, wherein

the memory device has a data read mode performed under the bias condition of:

a selected word line in the NAND string is applied with a read voltage;

the first dummy word line is applied with a first read pass voltage;

the second dummy word line and unselected word lines are applied with a second read pass voltage lower than the first read pass voltage; and

an erase-verify mode for erase-judging by detecting whether the bit line is charged-up to a certain level or not with cell current carried from the source line to the bit line.

10. A non-volatile semiconductor memory device comprising a NAND string, in which multiple memory cells are connected in series, one end of the NAND string being coupled to a bit line via a first select gate transistor while the other end is coupled to a source line via a second select gate transistor, first and second dummy cells being inserted in the NAND string to be disposed adjacent to the first and second select gate transistors, respectively, control gates of the memory cells and the first and second dummy cells being coupled to word lines and first and second dummy word lines, respectively, while gates of the first and second select gate transistors are coupled to first and second select gate lines, respectively, wherein

the memory device has a data read mode performed under the bias condition of:

a selected word line in the NAND string is applied with a read voltage;

the second dummy word line is applied with a first read pass voltage;

the first dummy word line and unselected word lines are applied with a second read pass voltage lower than the first read pass voltage; and

an erase-verify mode for erase-judging by detecting whether the bit line is lowered to a certain level or not with cell current carried from the bit line to the source line.

11. A non-volatile semiconductor memory device comprising a NAND string, in which multiple memory cells are connected in series, one end of the NAND string being coupled to a bit line via a first select gate transistor while the other end is coupled to a source line via a second select gate transistor, wherein

the memory device has a data read mode performed under the bias condition of:

a selected cell in the NAND string is applied with a read voltage; and

unselected cells in the NAND string are applied with read pass voltages set to turn on cells without regard to cell data;

an erase-verify mode for erase-judging by detecting whether the bit line is lowered to a certain level or not with cell current carried from the bit line to the source line under the condition that all cells in the NAND string are applied with a voltage equal to or higher than the ground potential;

the source line and a well on which the NAND string is formed are applied with a positive voltage;

the bit line is applied with a bit line voltage higher than the positive voltage;

the first select gate transistor is turned on; and

the second select gate transistor is turned on later than the first select gate transistor, and wherein

in the data read mode, the unselected cell adjacent to the second select gate transistor is applied with a first read pass voltage while the other unselected cells except unselected cells adjacent to the selected cell are applied with a second read pass voltage lower than the first read pass voltage.

12. The non-volatile semiconductor memory device according to claim 11, wherein

the unselected cell applied with the first read pass voltage is a dummy cell.

13. A non-volatile semiconductor memory device comprising a NAND string, in which multiple memory cells are connected in series, one end of the NAND string being coupled to a bit line via a first select gate transistor while the other end is coupled to a source line via a second select gate transistor, control gates of the memory cells being coupled to word lines, respectively, while gates of the first and second select gate transistors are coupled to first and second select gate lines, respectively, wherein

the memory device has a data read mode performed under the bias condition of:

a selected word line in the NAND string is applied with a read voltage;

an unselected word line adjacent to the second select gate line is applied with a first read pass voltage;

the other unselected word lines except unselected word lines adjacent to the selected word line are applied with a second read pass voltage lower than the first read pass voltage;

an erase-verify mode for erase-judging by detecting whether the bit line is lowered to a certain level or not with cell current carried from the bit line to the source line under the condition that all word lines in the NAND string are set at a voltage equal to or higher than the ground potential;

the source line and a well on which the NAND string is formed are applied with a positive voltage;

the bit line is applied with a bit line voltage higher than the positive voltage;

the first select gate transistor is turned on; and

the second select gate transistor is turned on later than the first select gate transistor.

14. The non-volatile semiconductor memory device according to claim 13, wherein

the unselected word line applied with the first read pass voltage is a dummy word line.