Offset compensation circuit and yaw rate sensor equipped therewith

• US 8,024,147 B2
• Filed: 11/12/2008
• Issued: 09/20/2011
• Est. Priority Date: 11/14/2007
• Status: Expired due to Fees

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Baus, Michael
• Primary Examiner(s): Wachsman; Hal
• Application Number:
  US12/269,616
• Publication Number:
  US 20090121769A1
• Time in Patent Office: 1,042 Days
• Field of Search: 702/33, 702/57, 702 86- 89, 702/104, 73/17.5, 73 178- 179, 73/18.8
• US Class Current: 702/104
• CPC Class Codes: G01C 25/005 initial alignment, calibration or starting-up of inertial devices
• CPC Class Codes: G01D 3/032 affecting incoming signal, e.g. by averaging; gating undesired signals
• CPC Class Codes: G01P 21/00 Testing or calibrating of apparatus or devices covered by the preceding groups

Abstract

An offset compensation circuit for a yaw rate sensor, having a subtracter, which is provided for subtracting a correction value from an input signal, the correction value being obtainable by dividing each of n measurements of the input signal by the constant n and subsequently integrating a number of n quotients into an integrator. Furthermore, a yaw rate sensor having such an offset compensation circuit.

Claims

1. An offset compensation circuit for a yaw rate sensor, comprising:

a subtracter for subtracting a correction value from an input signal of the yaw rate sensor, the correction value being a function of an average of n consecutive measurements of the input signal, wherein n is a number greater than 2.

2. The offset compensation circuit according to claim 1, further comprising:

an adder; and

a delay element, wherein the adder and the delay element are for providing an average by forming a sum of an input signal with an output signal of the adder, delayed by one cycle.

3. The offset compensation circuit according to claim 2, further comprising:

a device for setting the output signal of the adder to zero before adding a first input value.

4. The offset compensation circuit according to claim 2, further comprising:

an analog-digital converter for supplying the input signal.

5. The offset compensation circuit according to claim 1, wherein the number n is between 2 and 2048.

6. The offset compensation circuit according to claim 1, wherein the number n is 256.

7. The offset compensation circuit according to claim 1, wherein the number n corresponds to a power of two.

8. The offset compensation circuit according to claim 1, further comprising:

a low-pass filter for filtering at least one of the input signal and an output signal of the subtracter.

9. The offset compensation circuit according to claim 1, wherein an offset compensation runs once after a power supply is turned on or after a reset.

10. The offset compensation circuit according to claim 1, further comprising:

a trigger terminal for causing an offset compensation to run.

11. The offset compensation circuit according to claim 1, wherein the n measurements of the input signal are measured at respective n consecutive time cycles from the input signal.

12. The offset compensation circuit according to claim 1, further comprising:

an adder;

a delay element, wherein the adder and the delay element are for providing an average by forming a sum of the input signal with an output signal of the adder, delayed by one cycle;

a device for setting the output signal of the adder to zero before adding a first input value;

an analog-digital converter for supplying the input signal; and

a low-pass filter for filtering at least one of the input signal and an output signal of the subtracter;

wherein the number n is between 2 and 2048.

13. The offset compensation circuit according to claim 12, wherein the number n is 256.

14. The offset compensation circuit according to claim 12, wherein the number n corresponds to a power of two.

15. The offset compensation circuit according to claim 12, wherein an offset compensation runs once after a power supply is turned on or after a reset.

16. The offset compensation circuit according to claim 12, further comprising:

a trigger terminal for causing an offset compensation to run.

17. The offset compensation circuit according to claim 12, wherein the n measurements of the input signal are measured at respective n consecutive time cycles from the input signal.

18. A yaw rate sensor comprising:

an offset compensation circuit including a subtracter for subtracting a correction value from an input signal of the yaw rate sensor, the correction value being a function of an average of n consecutive measurements of the input signal, wherein n is a number greater than 2.

19. The yaw rate sensor according to claim 18, further comprising:

an adder; and

a delay element, wherein the adder and delay element are for providing an average by forming a sum of the input signal with an output signal of the adder, delayed by one cycle.

20. The yaw rate sensor according to claim 19, further comprising:

a device for setting the output signal of the adder to zero before adding a first input value.

21. The yaw rate sensor according to claim 19, further comprising:

an analog-digital converter for supplying the input signal.

22. The yaw rate sensor according to claim 18, wherein the number n is between 2 and 2048.

23. The yaw rate sensor according to claim 18, wherein the number n is 256.

24. The yaw rate sensor according to claim 18, wherein the number n corresponds to a power of two.

25. The yaw rate sensor according to claim 18, further comprising:

a low-pass filter for filtering at least one of the input signal and an output signal of the subtracter.

26. The yaw rate sensor according to claim 18, wherein an offset compensation runs once after a power supply is turned on or after a reset.

27. The yaw rate sensor according to claim 18, further comprising:

a trigger terminal for causing an offset compensation to run.

28. The yaw rate sensor according to claim 18, wherein the n measurements of the input signal are measured at respective n consecutive time cycles from the input signal.

29. The yaw rate sensor according to claim 18, further comprising:

an adder;

a delay element, wherein the adder and delay element are for providing an average by forming a sum of an input signal with an output signal of the adder, delayed by one cycle;

a device for setting the output signal of the adder to zero before adding a first input value;

an analog-digital converter for supplying the input signal;

a low-pass filter for filtering at least one of the input signal and an output signal of the subtracter;

wherein the number n is between 2 and 2048, and

wherein the n measurements of the input signal are measured at respective n consecutive time cycles from the input signal.

30. The yaw rate sensor according to claim 29, wherein the number n is 256.

31. The yaw rate sensor according to claim 29, wherein the number n corresponds to a power of two.

32. The yaw rate sensor according to claim 29, wherein an offset compensation runs once after a power supply is turned on or after a reset.

33. The yaw rate sensor according to claim 29, further comprising:

a trigger terminal for causing an offset compensation to run.

34. The yaw rate sensor according to claim 29, wherein the n measurements of the input signal are measured at respective n consecutive time cycles from the input signal.