Modifying an instruction stream using one or more bits to replace an instruction or to replace an instruction and to subsequently execute the replaced instruction
First Claim
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1. A processor, comprising:
- fetch logic adapted to fetch instructions from memory; and
decode logic coupled to said fetch logic and adapted to decode said fetched instructions;
wherein, if a bit in the decode logic is in a first state, a particular fetched instruction is skipped and a group of one or more instructions is executed in lieu of the particular fetched instruction;
wherein, if the bit is in a second state, said group is executed in lieu of the particular fetched instruction and said particular fetched instruction is executed after said group is executed.
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Abstract
A processor comprising fetch logic adapted to fetch instructions from memory and decode logic coupled to the fetch logic and adapted to decode the fetched instructions. If a bit in the decode logic is in a first state, a particular fetched instruction is skipped and a group of one or more instructions is executed in lieu of the particular fetched instruction. If the bit is in a second state, both the group and the particular fetched instruction are executed.
16 Citations
20 Claims
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1. A processor, comprising:
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fetch logic adapted to fetch instructions from memory; and decode logic coupled to said fetch logic and adapted to decode said fetched instructions; wherein, if a bit in the decode logic is in a first state, a particular fetched instruction is skipped and a group of one or more instructions is executed in lieu of the particular fetched instruction; wherein, if the bit is in a second state, said group is executed in lieu of the particular fetched instruction and said particular fetched instruction is executed after said group is executed. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An electronic device, comprising:
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decode logic adapted to decode instructions from an instruction storage unit, said decode logic comprising a data structure; wherein the data structure comprises a plurality of entries, each entry corresponding to a separate instruction and having; a first bit indicating whether a corresponding instruction is to be replaced by a micro-sequence comprising one or more secondary instructions; and a second bit indicating whether the micro-sequence is to be executed alone or in addition to the corresponding instruction; wherein, if the second bit indicates that the micro-sequence is to be executed in addition to the corresponding instruction, the micro-sequence is executed in lieu of the corresponding instruction and said corresponding instruction is executed after said micro-sequence is executed. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A method, comprising:
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if a bit in a processor is in a first state, executing a group comprising one or more secondary instructions in lieu of a primary instruction; and if the bit is in a second state, executing said group in lieu of the primary instruction and subsequently executing said primary instruction after executing said group. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification