Apparatus and method for testing semiconductor memory device

• US 8,024,628 B2
• Filed: 08/24/2009
• Issued: 09/20/2011
• Est. Priority Date: 07/29/2004
• Status: Expired due to Fees

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Do, Chang-Ho
• Primary Examiner(s): BRITT, CYNTHIA H
• Application Number:
  US12/546,600
• Publication Number:
  US 20090313513A1
• Time in Patent Office: 757 Days
• Field of Search: 714/718, 714/721, 365200-201
• US Class Current: 714/718
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 2029/1204 Bit line control
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: G11C 29/12005 comprising voltage or current generators

Abstract

A semiconductor memory device for performing a reliability test includes a write driving block for generating a predetermined test voltage in a test mode and delivering a data inputted from an external circuit into the local I/O line pair during a data access operation in a normal mode, a local I/O line pair coupled to the write driving block for receiving the predetermined test voltage in the test mode, and a cell array having a plurality of unit cells and a plurality of bit line pairs respectively having first and second bit lines and coupled to at least one unit cell for receiving the predetermined test voltage from each local I/O line pair to thereby check a result of the reliability test in the test mode.

Claims

1. A method for performing a background write test in the semiconductor memory device, comprising the steps of:

a) generating at least one test command signal;

b) preparing a test path for transmitting a predetermined test voltage outputted from an external circuit to a unit cell in response to the test command signal generated at the step a) by activating a word line for performing a test operation and by coupling a local input/output (I/O) line pair to a bit line for performing the test operation;

c) supplying the predetermined test voltage to the local I/O line pair; and

d) reading stored data of the unit cell in order to compare the predetermined test voltage with the stored data of the unit cell corresponding to the test path.

2. The method as recited in claim 1, wherein, in the step a), at least one test command signal is outputted from a test decision block in response to a test mode enable signal inputted from an external circuit.

3. The method as recited in claim 1, wherein the test decision block outputs one of two test mode signal set, four test mode signal set and eight test voltage control signal set according to a goal and a range of the background write test.

4. A semiconductor memory device for performing a background test, comprising:

a test decision block configured to determine a goal and a range of the background write test and to generate at least one test control signal;

a test voltage generating block configured to output at least one predetermined test voltage to each data line in response to the test control signal outputted from the test decision block, wherein the test voltage generating block activates a word line for performing a test operation and couples a local input/output (I/O) line pair to a bit line for performing the test operation; and

a test performing block, coupled to the test voltage generating block through each data line, configured to receive the predetermined test voltage and to compare the predetermined test voltage of each data line with stored data at each unit cell.

5. The semiconductor memory device as recited in claim 4, wherein the test decision block is enabled by a test mode enable signal inputted from an output side of the semiconductor memory device.

6. The semiconductor memory device as recited in claim 5, wherein the test decision block outputs one of two test mode signal set, four test mode signal set and eight test voltage control signal set according to the goal and the range of the background write test.

7. The semiconductor memory device as recited in claim 6, wherein the background test is carried out in one of a basis of even and odd number bit line pairs, a basis of a first and a second bit lines of each bit line pair and a basis of even and odd number bit line pairs and a first and a second bit lines of each bit line pairs according to the goal and the range of the background write test.

8. The semiconductor memory device as recited in claim 7, wherein a write driver for transmitting a data inputted from the outside of the semiconductor memory device into the local I/O line pair during a data access operation is served as the test voltage generating block during a test mode.

9. The semiconductor memory device as recited in claim 8, wherein the write driver includes:

a data receiving block for receiving the inputted data signal, a precharge command signal and a write enable signal and generating first and second output signals;

a latching block for receiving and latching the first and second output signals respectively to output an inverse first output signal and an inverse second output signal; and

the test voltage generating block for receiving the inverse first output signal, the inverse second output signal and first and second test mode signals to thereby output one of the inputted data signal and the predetermined test voltage to each local I/O line pair in response to the first and second test mode signals.

10. The semiconductor memory device as recited in claim 8, wherein the write driver includes:

a data receiving block for receiving the inputted data signal, a precharge command signal and a write enable signal and generating first and second output signals;

a latching block for receiving and latching the first and second output signals respectively to output an inverse first output signal and an inverse second output signal; and

a voltage generating block for receiving the inverse first output signal, the inverse second output signal, a first test mode signal, a second test mode signal, a third test mode signal and a fourth test mode signal to thereby output one of the inputted data signal and the predetermined test voltage to each local I/O line pair in response to the first to fourth test mode signals.

11. The semiconductor memory device as recited in claim 7, wherein a local I/O line precharging block for generating a core voltage as a local I/O line precharge voltage during a normal mode is served as the test voltage generating block during a test mode.

12. The semiconductor memory device as recited in claim 11, wherein the local I/O line precharging block includes:

a precharging block for precharging the local I/O line pair as the core voltage during the normal mode and outputting a logic high level voltage to the local I/O line pair in response to a first test control signal during the test mode;

a ground supplying block for outputting a logic low level voltage to the local I/O line pair in response to a second test control signal during the test mode; and

a control block for receiving a precharge command signal and the first test control signal to thereby control the precharging block during the normal mode and the test mode.

13. The semiconductor memory device as recited in claim 4, wherein the test performing block includes:

a cell array having a plurality of unit cells, each for storing an inputted data;

a sense amplifying block for sensing and amplifying a data stored in the cell array; and

a bit line pair for delivering the data between the cell array and the sense amplifying block.

14. The semiconductor memory device as recited in claim 13, wherein the data path include:

a segment I/O line pair, each having first and second segment I/O lines and each coupled to each bit line pair;

a first switching block for connecting or disconnecting each bit line pair to each segment I/O line pair in response to a first control signal;

a local I/O line pair, each having first and second local I/O lines and each coupled to each segment I/O pair; and

a second switching block for connecting or disconnecting each segment I/O line pair to each local I/O line pair in response to a second control signal,

wherein the first and second control signals are respectively corresponded to an address and a command signal inputted from the outside of the semiconductor memory device.

15. The semiconductor memory device as recited in claim 14, wherein the data line is the local I/O line pair.

16. The semiconductor memory device as recited in claim 14, wherein the data line is the segment I/O line pair.