Method and system for wafer topography-aware integrated circuit design analysis and optimization
First Claim
1. A method for designing an optimized specification of an integrated circuit, the integrated circuit comprising a plurality of cells, each of the plurality of cells comprising a plurality of devices, the method comprising:
- preparing a linewidth map of at least one device of the plurality of devices based on one or more defocus values indicative of thickness variation of the integrated circuit, a design layout of the integrated circuit, and a topography map of the integrated circuit;
performing a topography-aware analysis of the at least one device based on the linewidth map, one or more characterization models, and the topography map of the integrated circuit; and
designing an optimized specification of the integrated circuit with respect to one or more design objectives, based on the topography-aware analysis and subject to one or more design constraints, wherein each method operation is executed by a processor.
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Abstract
A method and system for designing an optimized specification of an integrated circuit (IC) is provided. The IC comprises a plurality of cells, and each of the cells comprises a plurality of transistors. The method includes preparing a linewidth map of at least one device of the plurality of devices, performing a topography-aware analysis of the at least one device based on the linewidth map, and designing the optimized specification of the IC based on the topography-aware analysis. In another embodiment, a method for estimating a leakage power of at least one device in an IC is provided. The method includes determining a defocus and a pitch value, determining a linewidth value based on the defocus and pitch value, and estimating the leakage current and/or leakage power based on the linewidth value.
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Citations
45 Claims
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1. A method for designing an optimized specification of an integrated circuit, the integrated circuit comprising a plurality of cells, each of the plurality of cells comprising a plurality of devices, the method comprising:
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preparing a linewidth map of at least one device of the plurality of devices based on one or more defocus values indicative of thickness variation of the integrated circuit, a design layout of the integrated circuit, and a topography map of the integrated circuit; performing a topography-aware analysis of the at least one device based on the linewidth map, one or more characterization models, and the topography map of the integrated circuit; and designing an optimized specification of the integrated circuit with respect to one or more design objectives, based on the topography-aware analysis and subject to one or more design constraints, wherein each method operation is executed by a processor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
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30. A system for designing an optimized specification of an integrated circuit, the integrated circuit comprising a plurality of cells, each of the plurality of cells comprising a plurality of devices, the system comprising:
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a mapping engine for preparing a linewidth map of at least one device of the plurality of devices based on one or more defocus values indicative of thickness variation of the integrated circuit, a topography map, and a design layout of the integrated circuit; an analysis engine for performing a topography-aware analysis of the at least one device based on the linewidth map, one or more characterization models, the design layout of the integrated circuit, and the topography map of the integrated circuit, and the topography map of the integrated circuit; and an optimization engine for designing an optimization specification of the integrated circuit with respect to one or more design objectives, based on the topography-aware analysis and one or more design constraints. - View Dependent Claims (31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45)
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Specification