Method of manufacturing printed wiring board with built-in electronic component

• US 8,024,858 B2
• Filed: 01/12/2009
• Issued: 09/27/2011
• Est. Priority Date: 02/14/2008
• Status: Active Grant

• Current Assignee: Ibiden Co., Ltd.
• Original Assignee: Ibiden Co., Ltd.
• Inventors: Tanaka, Hironori, Fujii, Naoaki, Yoshikawa, Kazuhiro, Yamashita, Atsunari
• Primary Examiner(s): PHAN, THIEM D
• Application Number:
  US12/351,954
• Publication Number:
  US 20090205202A1
• Time in Patent Office: 988 Days
• Field of Search: 298/52, 298/30, 298/32, 298/34, 298/37, 298/41, 298/46, 174/258, 174/260, 174/262, 174/264, 361/761, 361/764
• US Class Current: 29/852
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/82039 using a laser
• CPC Class Codes: H01L 2224/82047 by mechanical means, e.g. severing, pressing, stamping
• CPC Class Codes: H01L 2224/83132 using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
• CPC Class Codes: H01L 2224/92144 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01012 Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3511 : Warping
• CPC Class Codes: H05K 1/036 : Multilayers with layers of different types
• CPC Class Codes: H05K 1/185 : Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 1/188 : manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
• CPC Class Codes: H05K 2201/0352 : Differences between the conductors of different layers of a multilayer
• CPC Class Codes: H05K 2201/09509 : Blind vias, i.e. vias having one side closed
• CPC Class Codes: H05K 2201/09536 : Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
• CPC Class Codes: H05K 2201/0969 : Apertured conductors
• CPC Class Codes: H05K 2201/09918 : Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components
• CPC Class Codes: H05K 2201/10636 : Leadless chip, e.g. chip capacitor or resistor
• CPC Class Codes: H05K 3/426 : initial plating of through-holes in substrates without metal
• CPC Class Codes: H05K 3/427 : initial plating of through-holes in metal-clad substrates
• CPC Class Codes: H05K 3/4602 : characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
• CPC Class Codes: H05K 3/4611 : by laminating two or more circuit boards H05K3/4652 takes precedence
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product
• CPC Class Codes: Y10T 29/49117 : Conductor or circuit manufacturing
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49133 : with component orienting
• CPC Class Codes: Y10T 29/49146 : with encapsulating, e.g., potting, etc.
• CPC Class Codes: Y10T 29/49165 : by forming conductive walled aperture in base

Abstract

A printed wiring board is manufactured by a method in which a base substrate having a first insulation layer, a second insulation layer, and a conductive film is provided. An electronic component is placed on the first insulation layer at a position determined based on an alignment mark. After the electronic component is enclosed inside an opening of the second insulation layer, a via hole exposing a terminal of the electronic component is formed at a position determined based on the alignment mark, which is used to determine the position of the electronic component. A via conductor is formed in the via hole, and a conductive layer is formed on the conductive film and patterned to form a conductive circuit connected to the via conductor.

Claims

1. A method of manufacturing a printed wiring board, comprising:

providing a base substrate comprising a first insulation layer, a second insulation layer, and a conductive film, wherein the conductive film is provided on a first surface of the first insulation layer, the second insulation layer is provided on a second surface opposite to the first surface of the first insulation layer, and the second insulation layer has an opening for enclosing an electronic component;

forming an alignment mark by removing at least a portion of the conductive film;

providing an adhesive layer on the second surface of the first insulation layer at a position being exposed through the opening of the second insulation layer and determined based on the alignment mark;

placing the electronic component on the adhesive layer at a position determined based on the alignment mark;

forming a third insulation layer on the second insulation layer to enclose the electronic component inside the opening of the second insulation layer;

forming a via hole to penetrate the conductive film and the first insulation layer, the via hole being formed at a position determined based on the alignment mark, and the via hole exposing a terminal of the electronic component;

plating a surface of the conductive film and a surface of the via hole to form a via conductor in the via hole and to form a conductive layer on the conductive film, the via conductor being connected to the terminal of the electronic component; and

patterning the conductive layer to form a conductive circuit connected to the via conductor.

2. The method of claim 1, wherein providing the base substrate comprises:

providing a laminate body having the conductive film and the first insulation layer;

preparing the second insulation layer having the opening for enclosing the electronic component; and

providing the second insulation layer on the laminate body such that the second surface of the first insulation layer faces the first surface of the second insulation layer.

3. The method of claim 2, wherein providing the base substrate includes thermopressing the laminate body and an uncured resin material to be the second insulation layer.

4. The method of claim 2, wherein providing the base substrate includes thermopressing the laminate body, an uncured resin material, and a cured resin material to be the second insulation layer.

5. The method of claim 2, wherein the laminate body comprises a single-sided copper-clad laminate.

6. The method of claim 1, wherein providing the base substrate includes thermopressing the conductive film, an uncured resin material to be the first insulation layer, and a cured resin material to be the second insulation layer.

7. The method of claim 1, wherein forming the third insulation layer comprises thermopressing the base substrate, an uncured resin material to be the third insulation layer, and the electronic component to press out the uncured resin material from the third insulation layer, fill a space inside the opening with the resin material and cure the resin material to fix the electronic component inside the opening.

8. The method of claim 1, further comprising providing a filler inside the opening to fix the electronic component therein, wherein the filler comprises a thermosetting resin and at least one inorganic filler selected from a group consisting of Al₂O₃, MgO, BN, AlN and SiO₂.

9. The method of claim 8, wherein the filler comprises about 30 wt. % to about 60 wt. % inorganic filler.

10. The method of claim 1, wherein forming the alignment mark comprises forming a through-hole that penetrates the conductive film, the first insulation layer, and the second insulation layer.

11. The method of claim 1, wherein forming the alignment mark comprises forming a through-hole that penetrates the conductive film, the first insulation layer, and the second insulation layer.

12. The method of claim 1, wherein forming the alignment mark comprises forming a conductive portion and an insulative portion surrounding the conductive portion, and the insulative portion is a part of the first insulative layer exposed by removing a part of the conductive film.

13. The method of claim 1, wherein forming the via hole includes applying a laser to penetrate the conductive film and the first insulation layer.

14. The method of claim 1, wherein forming the via conductor includes forming an electroless plated film on the surface of the via hole and forming an electrolytic plated film on the electroless plated film.

15. The method of claim 1, wherein the conductive film comprises copper foil.

16. The method of claim 1, further comprising:

forming a through-hole penetrating the conductive film, the first insulation layer, the second insulation layer, and the third insulation layer; and

forming a through-hole conductor in the through-hole.

17. The method of claim 16, wherein forming the through-hole conductor includes connecting the conductive film to the through-hole conductor.