Semiconductor device and structure

• US 8,026,521 B1
• Filed: 10/11/2010
• Issued: 09/27/2011
• Est. Priority Date: 10/11/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Sekar, Deepak C., Or-Bach, Zvi
• Primary Examiner(s): Kebede; Brook
• Application Number:
  US12/901,890
• Time in Patent Office: 351 Days
• Field of Search: 438149-167, 438/238, 438/239, 438257-267, 438/386, 438/396, 257 67- 71, 257/304, 257/308, 257/312, 257/905, 257/E27.084, 257/E21.646
• US Class Current: 257/67
• CPC Class Codes: H01L 2029/7857 of the accumulation type
• CPC Class Codes: H01L 21/268 using electromagnetic radiation, e.g. laser radiation
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/36 the transistor being a FinFET
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 : of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 61/22 : of the field-effect transistor [FET] type
• CPC Class Codes: H10B 63/30 : comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/84 : arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10B 63/845 : the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/20 : Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/823 : adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx

Abstract

A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.

Claims

1. A device comprising semiconductor memories, the device comprising:

a first monocrystalline silicon transferred layer;

a second monocrystalline silicon transferred layer;

wherein said first monocrystalline silicon transferred layer comprises a first plurality of horizontally-oriented transistors;

wherein said second monocrystalline silicon transferred layer comprises a second plurality of horizontally-oriented transistors; and

wherein said second plurality of horizontally-oriented transistors overlays said first plurality of horizontally-oriented transistors.

2. A device according to claim 1, further comprising:

a plurality of a memory cell control lines embedded within said first monocrystalline silicon transferred layer and said second monocrystalline silicon transferred layer.

3. A device according to claim 1, wherein said first plurality of horizontally-oriented transistors and said second plurality of horizontally-oriented transistors have side gates.

4. A device according to claim 1, wherein said semiconductor memories are dynamic random access memory (DRAM) type memory.

5. A device according to claim 1, wherein said semiconductor memories are charge-trap type memory.

6. A device according to claim 1, wherein said semiconductor memories are floating-gate type memory.

7. A device according to claim 1, wherein said semiconductor memories are resistive-random-access memory (RAM) type memory.

8. A device according to claim 1, wherein said semiconductor memories are phase-change type memory.

9. A device comprising semiconductor memories, the device comprising:

a first monocrystalline silicon transferred layer;

a second monocrystalline silicon transferred layer, wherein said first monocrystalline silicon transferred layer comprises a first plurality of horizontally-oriented transistors;

wherein said second monocrystalline silicon transferred layer comprises a second plurality of horizontally-oriented transistors;

wherein said first monocrystalline silicon transferred layer further comprises a first plurality of select lines as memory cell control lines, and wherein said second monocrystalline silicon transferred layer further comprises a second plurality of select lines as memory cell control lines.

10. A device according to claim 9, wherein said second plurality of horizontally-oriented transistors overlays said first plurality of horizontally-oriented transistors.

11. A device according to claim 9, wherein said first plurality of horizontally-oriented transistors and said second plurality of horizontally-oriented transistors have side gates.

12. A device according to claim 9, wherein said semiconductor memories are DRAM type memory.

13. A device according to claim 9 wherein said semiconductor memories are resistive-RAM type memory.

14. A device according to claim 9, wherein said semiconductor memories are phase-change type memory.

15. A device comprising semiconductor memories, said device comprising:

a first monocrystalline silicon transferred layer;

a second monocrystalline silicon transferred layer, wherein said first monocrystalline silicon transferred layer comprises a first plurality of horizontally-oriented transistors;

wherein said second monocrystalline silicon transferred layer comprises a second plurality of horizontally-oriented transistors;

wherein said first plurality of horizontally-oriented transistors and said second plurality of horizontally-oriented transistors have side gates.

16. A device according to claim 15, further comprising:

a plurality of a memory cell control lines embedded within said first layer and said second layer.

17. A device according to claim 15, wherein said second plurality of horizontally-oriented transistors overlays said first plurality of horizontally-oriented transistors.

18. A device according to claim 15, wherein said semiconductor memories are DRAM type memory.

19. A device according to claim 15, wherein said semiconductor memories are resistive-RAM type memory.

20. A device according to claim 15, wherein said semiconductor memories are phase-change type memory.