Method of wire bonding over active area of a semiconductor circuit

• US 8,026,588 B2
• Filed: 02/16/2007
• Issued: 09/27/2011
• Est. Priority Date: 10/15/2002
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Chen, Ying-Chih, Lin, Mou-Shiung, Lee, Jin-Yuan
• Primary Examiner(s): Smith; Zandra
• Assistant Examiner(s): Chiu; Tsz K
• Application Number:
  US11/707,827
• Publication Number:
  US 20070273031A1
• Time in Patent Office: 1,684 Days
• Field of Search: 257/737, 257/738, 257/778, 257/E23.021, 257/E23.132, 257/E21.508, 257/E21.579, 257/E23.02, 438/612
• US Class Current: 257/690
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05073 Single internal layer
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05187 Ceramics, e.g. crystalline carbides, nitrides or oxides glass ceramics H01L2224/05188
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/4807 of bonding interfaces, e.g. interlocking features
• CPC Class Codes: H01L 2224/48453 of the interface with the bonding area
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/48599 Principal constituent of the connecting portion of the wire connector being Gold (Au)
• CPC Class Codes: H01L 2224/48624 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48644 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48647 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/854 : with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/85424 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/85444 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/85447 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01007 : Nitrogen [N]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

Claims

1. An integrated circuit die comprising:

a semiconductor substrate;

a dielectric layer over said semiconductor substrate;

a metallization structure over said dielectric layer;

a passivation layer over said dielectric layer and over said metallization structure, wherein said passivation layer comprises a nitride, wherein a first opening in said passivation layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of said first opening;

a polymer structure on said passivation layer, wherein said polymer structure is not vertically over said first contact point, wherein said polymer structure has a top, a first sidewall and a second sidewall opposite to said first sidewall, wherein said top is between said first and second sidewalls; and

a metal layer on said top, on said first and second sidewalls and on said first contact point, wherein said metal layer comprises a first portion on said first sidewall, a second portion on said second sidewall and a third portion on said top, wherein said third portion of said metal layer has a bonding contact area vertically over said top, wherein said bonding contact area is connected to said first contact point through said first opening, wherein said first portion of said metal layer is connected to said second portion of said metal layer through said third portion of said metal layer, wherein said metal layer comprises a titanium-containing layer and a first gold layer directly on said titanium-containing layer, wherein no polymer layer is on said metal layer.

2. The integrated circuit die of claim 1, wherein said metal layer further comprises a second gold layer directly on said first gold layer.

3. The integrated circuit die of claim 2, wherein said second gold layer has a thickness greater than 1 micrometer.

4. The integrated circuit die of claim 1, wherein said polymer structure comprises polyimide.

5. The integrated circuit die of claim 1, wherein said polymer structure comprises benzocyclobutene (BCB).

6. The integrated circuit die of claim 1, wherein said titanium-containing layer comprises a titanium-tungsten-alloy layer.

7. The integrated circuit die of claim 1, wherein a second opening in said passivation layer is over a second contact point of said metallization structure, and said second contact point is at a bottom of said second opening, wherein said bonding contact area is connected to said second contact point through said second opening, wherein said first contact point is connected to said second contact point through said metal layer.

8. The integrated circuit die of claim 1, wherein said passivation layer further comprises an oxide.

9. The integrated circuit die of claim 1, wherein said metal layer is further on said passivation layer.

10. The integrated circuit die of claim 1, wherein said metal layer has a first top region vertically over said top and a second top region vertically over said first contact point, wherein said first top region is at a horizontal level higher than said second top region.

11. The integrated circuit die of claim 1, wherein said bonding contact area is configured to be wirebonded thereto.

12. The integrated circuit die of claim 1, wherein said polymer structure has a first width at said top and a second width at a bottom of said polymer structure, wherein said first width is less than said second width.

13. The integrated circuit die of claim 2, wherein said second gold layer is electroplated.

14. The integrated circuit die of claim 1, wherein said polymer structure has a thickness of at least 2 micrometers.

15. The integrated circuit die of claim 1, wherein said first sidewall has a slope with an angle between 50 and 60 degrees.

16. The integrated circuit die of claim 1, wherein said dielectric layer has a dielectric constant less than 3.0.

17. An integrated circuit die comprising:

a semiconductor substrate;

a dielectric layer over said semiconductor substrate;

a metallization structure over said dielectric layer;

a passivation layer over said dielectric layer and over said metallization structure, wherein said passivation layer comprises a nitride, wherein a first opening in said passivation layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of said first opening;

a polymer structure on said passivation layer, wherein said polymer structure has a top, a first sidewall and a second sidewall opposite to said first sidewall, wherein said top is between said first and second sidewalls; and

a metal layer on said top, on said first and second sidewalls and on said first contact point, wherein said metal layer comprises a first portion on said first sidewall, a second portion on said second sidewall and a third portion on said top, wherein said third portion of said metal layer has a bonding contact area vertically over said top, wherein said bonding contact area is connected to said first contact point through said first opening, wherein said first portion of said metal layer is connected to said second portion of said metal layer through said third portion of said metal layer, wherein said metal layer comprises a first gold layer and a second gold layer directly on said first gold layer.

18. The integrated circuit die of claim 17, wherein said metal layer further comprises a titanium-tungsten-alloy layer under said first gold layer.

19. The integrated circuit die of claim 17, wherein said second gold layer has a thickness greater than 1 micrometer.

20. The integrated circuit die of claim 17, wherein said polymer structure comprises polyimide.

21. The integrated circuit die of claim 17, wherein said polymer structure comprises benzocyclobutene (BCB).

22. The integrated circuit die of claim 17, wherein said metal layer further comprises a titanium-nitride layer under said first gold layer.

23. The integrated circuit die of claim 17, wherein a second opening in said passivation layer is over a second contact point of said metallization structure, and said second contact point is at a bottom of said second opening, wherein said bonding contact area is connected to said second contact point through said second opening, wherein said first contact point is connected to said second contact point through said metal layer.

24. The integrated circuit die of claim 17, wherein said passivation layer further comprises an oxide.

25. The integrated circuit die of claim 17, wherein said metal layer is further on said passivation layer.

26. The integrated circuit die of claim 17, wherein said metal layer has a first top region vertically over said top and a second top region vertically over said first contact point, wherein said first top region is at a horizontal level higher than said second top region.

27. The integrated circuit die of claim 17, wherein said bonding contact area is configured to be wirebonded thereto.

28. The integrated circuit die of claim 17, wherein said polymer structure has a first width at said top and a second width at a bottom of said polymer structure, wherein said first width is less than said second width.

29. The integrated circuit die of claim 17, wherein said second gold layer is electroplated.

30. The integrated circuit die of claim 17, wherein no polymer layer is on said metal layer.

31. The integrated circuit die of claim 17, wherein said polymer structure is not vertically over said first contact point.

32. The integrated circuit die of claim 17, wherein said polymer structure has a thickness of at least 2 micrometers.

33. The integrated circuit die of claim 17, wherein said first sidewall has a slope with an angle between 50 and 60 degrees.

34. The integrated circuit die of claim 17, wherein said dielectric layer comprises silicon, oxygen and carbon.

50. The integrated circuit die of claim 23, wherein no polymer layer is on said metal layer.

51. The integrated circuit die of claim 23, wherein said polymer structure is not vertically over said first and second contact points.

52. The integrated circuit die of claim 23, wherein said polymer structure has a thickness of at least 2 micrometers.

53. The integrated circuit die of claim 23, wherein said first sidewall has a slope with an angle between 50 and 60 degrees.

35. An integrated circuit die comprising:

a semiconductor substrate;

a dielectric layer over said semiconductor substrate;

a metallization structure over said dielectric layer;

a passivation layer over said dielectric layer and over said metallization structure, wherein said passivation layer comprises a nitride, wherein a first opening in said passivation layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of said metallization structure, and said second contact point is at a bottom of said second opening;

a polymer structure on said passivation layer, wherein said polymer structure has a top, a first sidewall and a second sidewall opposite to said first sidewall, wherein said top is between said first and second sidewalls; and

a metal layer on said top, on said first and second sidewalls and on said first and second contact points, wherein said metal layer has a bonding contact area vertically over said top, wherein said bonding contact area is connected to said first contact point through said first opening, and wherein said bonding contact area is connected to said second contact point through said second opening, wherein said first contact point is connected to said second contact point through said metal layer, wherein said metal layer comprises a titanium-containing layer, a gold seed layer on said titanium-containing layer, and an electroplated gold layer on said gold seed layer.

36. The integrated circuit die of claim 35, wherein said titanium-containing layer comprises titanium nitride.

37. The integrated circuit die of claim 35, wherein said electroplated gold layer has a hardness less than 150 Hv.

38. The integrated circuit die of claim 35, wherein said dielectric layer has a dielectric constant less than 3.0.

39. The integrated circuit die of claim 35, wherein said electroplated gold layer has a thickness greater than 1 micrometer.

40. The integrated circuit die of claim 35, wherein said metal layer has a first top region vertically over said top, a second top region vertically over said first contact point and a third top region vertically over said second contact point, wherein said first top region is at a horizontal level higher than said second and third top regions.

41. The integrated circuit die of claim 35, wherein said titanium-containing layer comprises a titanium-tungsten alloy.

42. The integrated circuit die of claim 35, wherein said polymer structure has a first width at said top and a second width at a bottom of said polymer structure, wherein said first width is less than said second width.

43. The integrated circuit die of claim 35, wherein said polymer structure comprises polyimide.

44. The integrated circuit die of claim 35, wherein said polymer structure comprises benzocyclobutene (BCB).

45. The integrated circuit die of claim 35, wherein said nitride comprises silicon nitride.

46. The integrated circuit die of claim 35, wherein said passivation layer further comprises an oxide.

47. The integrated circuit die of claim 46, wherein said oxide comprises silicon oxide.

48. The integrated circuit die of claim 35, wherein said bonding contact area is configured to be wirebonded thereto.

49. The integrated circuit die of claim 35, wherein said metal layer is further on said passivation layer.

54. An integrated circuit die comprising:

a semiconductor substrate;

a dielectric layer over said semiconductor substrate;

a metallization structure over said dielectric layer;

a passivation layer over said dielectric layer and over said metallization structure, wherein said passivation layer comprises a nitride, wherein a first opening in said passivation layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of said first opening;

a polymer structure on a first region of a top surface of said passivation layer, wherein said polymer structure has a top, a first sidewall and a second sidewall opposite to said first sidewall, wherein said top is between said first and second sidewalls and is not vertically over said first contact point; and

a metal layer on said top, on said first and second sidewalls, on said first contact point and on a second region of said top surface of said passivation layer, wherein said second region is between said first region and said first opening, wherein said metal layer comprises a first portion on said first sidewall, a second portion on said second sidewall and a third portion on said top, wherein said third portion of said metal layer has a bonding contact area vertically over said top, wherein said bonding contact area is connected to said first contact point through said first opening, wherein said first portion of said metal layer is connected to said second portion of said metal layer through said third portion of said metal layer, wherein said metal layer comprises a glue layer and a gold layer over said glue layer, wherein no polymer layer is on said metal layer.

55. The integrated circuit die of claim 54, wherein said gold layer has a thickness less than that of said passivation layer.

56. The integrated circuit die of claim 54, wherein said polymer structure comprises polyimide.

57. The integrated circuit die of claim 54, wherein said glue layer comprises a titanium-containing layer.

58. The integrated circuit die of claim 54, wherein a second opening in said passivation layer is over a second contact point of said metallization structure, and said second contact point is at a bottom of said second opening, wherein said bonding contact area is connected to said second contact point through said second opening, wherein said first contact point is connected to said second contact point through said metal layer.

59. The integrated circuit die of claim 54, wherein said dielectric layer comprises silicon, oxygen and carbon.

60. The integrated circuit die of claim 54, wherein said polymer structure has a thickness of at least 2 micrometers.

61. The integrated circuit die of claim 54, wherein said first sidewall has a slope with an angle between 50 and 60 degrees.

62. An integrated circuit die comprising:

a semiconductor substrate;

a dielectric layer over said semiconductor substrate;

a first metal interconnect over said dielectric layer;

a passivation layer over said dielectric layer and over said first metal interconnect, wherein a first opening in said passivation layer is over a first contact point of said first metal interconnect, and said first contact point is at a bottom of said first opening;

a polymer structure on a first region of a top surface of said passivation layer, wherein said polymer structure has a right slope surface and a left slope surface opposite to said right slope surface; and

a metal layer on said right and left slope surfaces, on said first contact point and on a second region of said top surface of said passivation layer, wherein said second region is between said first region and said first opening, wherein said metal layer is connected to said first contact point through said first opening, wherein said metal layer comprises a first portion on said right slope surface and a second portion on said left slope surface, wherein said first portion of said metal layer is connected to said second portion of said metal layer, wherein said metal layer has a bonding contact area vertically over a portion of said polymer structure between said right and left slope surfaces, wherein said bonding contact area is connected to said first contact point through said second portion of said metal layer, wherein said metal layer comprises a glue layer and a gold layer over said glue layer.

63. The integrated circuit die of claim 62, wherein said gold layer has a thickness less than that of said passivation layer.

64. The integrated circuit die of claim 62, wherein said gold layer contacts said glue layer.

65. The integrated circuit die of claim 62, wherein said gold layer comprises electroplated gold.

66. The integrated circuit die of claim 62, wherein said glue layer comprises a titanium-containing layer.

67. The integrated circuit die of claim 62 further comprising a second metal interconnect over said dielectric layer, wherein a second opening in said passivation layer is over a second contact point of said second metal interconnect, and said second contact point is at a bottom of said second opening, wherein said metal layer is connected to said second contact point through said second opening, wherein said bonding contact area is connected to said second contact point through said first portion of said metal layer, wherein said first contact point is connected to said second contact point through said first and second portions of said metal layer.

68. The integrated circuit die of claim 67, wherein said first metal interconnect has a portion spaced apart from a portion of said second metal interconnect, wherein said portion of said first metal interconnect comprises said first contact point, and wherein said portion of said second metal interconnect comprises said second contact point.

69. The integrated circuit die of claim 62, wherein said dielectric layer comprises silicon, oxygen and carbon.

70. The integrated circuit die of claim 62, wherein said polymer structure has a thickness of at least 2 micrometers.

71. The integrated circuit die of claim 62, wherein said left slope surface has a slope with an angle between 50 and 60 degrees.

72. The integrated circuit die of claim 62, wherein said passivation layer comprises a nitride.

73. The integrated circuit die of claim 62, wherein no polymer layer is on said metal layer.

74. The integrated circuit die of claim 62, wherein said left slope surface has a positive slope, and said right slope surface has a negative slope.