Reduced profile stackable semiconductor package

• US 8,026,589 B1
• Filed: 02/23/2009
• Issued: 09/27/2011
• Est. Priority Date: 02/23/2009
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Kim, Do Hyung, Kang, Won Joon, Sohn, Eun Sook, Lee, Min Woo, Hwang, Chan Ha, Kim, Bong Chan
• Primary Examiner(s): DANG, PHUC T
• Application Number:
  US12/390,999
• Time in Patent Office: 946 Days
• Field of Search: 257/686, 257/690, 257/693, 438/126, 438/617
• US Class Current: 257/690
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/48471 the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
• CPC Class Codes: H01L 2224/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83101 as prepeg comprising a layer connector, e.g. provided in an insulating plate member
• CPC Class Codes: H01L 2224/85001 involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
• CPC Class Codes: H01L 2224/8592 Applying permanent coating, e.g. protective coating
• CPC Class Codes: H01L 2224/92247 : the second connecting process involving a wire connector
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1029 : the support being a lead frame
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1041 : Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/107 : Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/49517 : Additional leads
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01083 : Bismuth [Bi]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/078 : Adhesive characteristics other than chemical
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape

Abstract

In accordance with the present invention, there is provided multiple embodiments of a reduced profile stackable semiconductor package. The semiconductor package comprises a substrate having at least one semiconductor die attached thereto. The semiconductor die is also electrically connected to the substrate by a plurality of conductive wires. A package body defining opposed top and bottom surfaces and a side surface at least partially encapsulates the substrate, the conductive wires and the semiconductor die. The package body is formed such that at least portions of the conductive wires are exposed in the top surface thereof. The package body may include a groove formed in the top surface thereof, with at least portions of the conductive wires being exposed in the groove. In this instance, conductive material layers may be disposed within the groove and electrically connected to the exposed portions of respective ones of the conductive wires, with solder pads further bring electrically connected to respective ones of the conductive material layers and at least partially residing within the groove.

Claims

1. A semiconductor package comprising:

a substrate;

at least one semiconductor die attached to the substrate and electrically connected thereto by at least one conductive wire; and

a package body defining a generally planar top surface, a bottom surface, and a side surface, the package body at least partially encapsulating the substrate, the conductive wire and the semiconductor die, and being formed such that at least a portion of the conductive wire is exposed in the top surface thereof.

2. The semiconductor package of claim 1 further comprising a conductive material layer disposed on the top surface of the package body and electrically connected to the exposed portion of the conductive wire.

3. The semiconductor package of claim 2 wherein:

the semiconductor die is electrically connected to the substrate by a plurality of conductive wires, each of which includes a portion which is exposed in the top surface of the package body; and

a plurality of conductive material layers are disposed on the top surface of the package body and electrically connected to the exposed portions of respective ones of the conductive wires.

4. The semiconductor package of claim 3 further in combination with a semiconductor device which is stacked upon the semiconductor package and electrically connected to the conductive material layers thereof.

5. The semiconductor package of claim 4 wherein the semiconductor device stacked upon and electrically connected to the semiconductor package comprises one of another semiconductor package and a semiconductor die.

6. The semiconductor package of claim 5 wherein the semiconductor device comprises a second semiconductor package which is identically configured to the semiconductor package, the second semiconductor package being electrically connected to the conductive material layers of the semiconductor package.

7. The semiconductor package of claim 1 wherein the substrate comprises a leadframe including:

a die pad defining opposed top and bottom pad surfaces; and

a plurality of leads which each define opposed top and bottom lead surfaces and extend at least partially about the die pad in spaced relation thereto;

the semiconductor die being attached to the top pad surface of the die pad and electrically connected to at least some the leads by a plurality of the conductive wires, each of which includes a portion which is exposed in the top surface of the package body which is formed such that that the bottom pad surfaces and the bottom lead surfaces are exposed therein.

8. The semiconductor package of claim 1 wherein the substrate comprises:

an insulative layer defining opposed top and bottom surfaces; and

first and second conductive patterns disposed on respective ones of the top and bottom surfaces of the insulative layer and electrically connected to each other in a prescribed pattern;

the semiconductor die being attached to the top surface of the insulative layer and electrically connected to the first conductive pattern by the conductive wire.

9. A semiconductor package comprising:

a semiconductor die;

a plurality of conductive pads at least partially circumventing the semiconductor die and electrically connected thereto by at least one conductive wire; and

a package body defining a generally planar top surface, a bottom surface, and a side surface, the package body at least partially encapsulating the semiconductor die, the conductive pads and the conductive wire, and being formed such that at least a portion of the conductive wire is exposed in the top surface thereof.

10. The semiconductor package of claim 9 further comprising at least one conductive material layer electrically connected to the exposed portion of the conductive wire.

11. A semiconductor package comprising:

a die pad defining opposed top and bottom pad surfaces;

a plurality of leads which each define opposed top and bottom lead surfaces and extend at least partially about the die pad in spaced relation thereto;

at least one semiconductor die attached to the top pad surface of the die pad and electrically connected to at least some the leads by conductive wires; and

a package body defining opposed top and bottom surfaces, a side surface, and a groove formed in the top surface, the package body at least partially encapsulating the substrate, the conductive wires and the semiconductor die, and being formed such that at least portions of the conductive wires are exposed in the groove.

12. The semiconductor package of claim 11 further comprising a plurality of conductive material layers which are disposed within the groove and electrically connected to the exposed portions of respective ones of the conductive wires.

13. The semiconductor package of claim 12 further comprising a plurality of solder pads which are electrically connected to respective ones of the conductive material layers and sized to protrude from the top surface of the package body.

14. The semiconductor package of claim 13 further in combination with a semiconductor device which is stacked upon the semiconductor package and electrically connected to the solder pads thereof.

15. The semiconductor package of claim 14 wherein the semiconductor device stacked upon and electrically connected to the semiconductor package comprises one of another semiconductor package and a semiconductor die.

16. The semiconductor package of claim 15 wherein the semiconductor device comprises a second semiconductor package which is identically configured to the semiconductor package, the second semiconductor package having bottom lead surfaces which are electrically connected to respective ones of the solder pads of the semiconductor package.

17. The semiconductor package of claim 14 wherein the semiconductor device is electrically connected to the solder pads of the semiconductor package through the use of an intervening interposer.

18. A semiconductor package comprising:

an insulative layer defining opposed top and bottom surfaces; and

first and second conductive patterns disposed on respective ones of the top and bottom surfaces of the insulative layer and electrically connected to each other in a prescribed pattern;

at least one semiconductor die attached to the top surface of the insulative layer and electrically connected to the first conductive pattern by at least one conductive wire; and

a package body defining opposed top and bottom surfaces, a side surface, and a groove formed in the top surface, the package body at least partially encapsulating the substrate, the conductive wire and the semiconductor die, and being formed such that at least a portion of the conductive wire is exposed in the groove.

19. The semiconductor package of claim 18 further comprising a conductive material layer disposed within the groove and electrically connected to the exposed portion of the conductive wire.

20. The semiconductor package of claim 19 further comprising a solder pad electrically connected to the conductive material layer and at least partially residing within the groove.

21. The semiconductor package of claim 20 wherein:

the semiconductor die is electrically connected to the first conductive pattern by a plurality of conductive wires, each of which includes a portion which is exposed in the groove;

a plurality of conductive material layers are disposed within the groove and electrically connected to the exposed portions of respective ones of the conductive wires; and

a plurality of solder pads are electrically connected to the respective ones of the conductive material layers and sized to protrude from the top surface of the package body.

22. The semiconductor package of claim 21 further in combination with a semiconductor device which is stacked upon the semiconductor package and electrically connected to the solder pads thereof.

23. The semiconductor package of claim 22 wherein the semiconductor device stacked upon and electrically connected to the semiconductor package comprises one of another semiconductor package and a semiconductor die.

24. The semiconductor package of claim 23 wherein the semiconductor device comprises a second semiconductor package which is identically configured to the semiconductor package, the bottom lead surfaces of the second semiconductor package being electrically connected to respective ones of the solder pads of the semiconductor package.

25. The semiconductor package of claim 22 wherein the semiconductor device is electrically connected to the solder pads of the semiconductor package through the use of an intervening interposer.