System level interconnect with programmable switching

• US 8,026,739 B2
• Filed: 12/27/2007
• Issued: 09/27/2011
• Est. Priority Date: 04/17/2007
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Sullam, Bert, Snyder, Warren, Mohammed, Haneef
• Primary Examiner(s): TRAN, ANH Q
• Application Number:
  US11/965,677
• Publication Number:
  US 20080258760A1
• Time in Patent Office: 1,370 Days
• Field of Search: None
• US Class Current: 326/39
• CPC Class Codes: H03K 19/173 using elementary logic circuits as components
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/1776 for memories

Abstract

Different functional elements are all located on a same integrated circuit wherein at least one of the functional elements comprises a micro-controller. Configuration registers or configuration memory in the integrated circuit store configuration values loaded by the micro-controller. Connectors are configured to connect the integrated circuit to external signals. A system level interconnect also located in the integrated circuit programmably connects together the different functional elements and different connectors according to the configuration values loaded into the configuration registers.

Claims

1. An apparatus, comprising:

different functional elements all located in a same integrated circuit wherein at least one of the functional elements comprises a micro-controller;

configuration registers or configuration memory in the integrated circuit to store configuration values loaded by the micro-controller;

different connectors configured to connect the integrated circuit to external signals; and

a system level interconnect located in the integrated circuit configured to programmably connect any of the different functional elements to any of the different connectors and to connect any of the different functional elements to each other according to the configuration values loaded into the configuration registers or configuration memory by the micro-controller.

2. The apparatus according to claim 1 wherein the system level interconnect dynamically changes the connections between the different functional elements and the different connectors in real time according to different operational states of the integrated circuit.

4. The apparatus according to claim 1 wherein:

the functional elements further include multiple digital blocks that each include programmable logic device sections having uncommitted user programmable logic functions and datapath sections having structural arithmetic elements that together form an arithmetic sequencer; and

the system level interconnect is programmably configurable to connect different selectable programmable logic device sections in the digital blocks to other different selectable functional elements and to different selectable connectors; and

the system level interconnect is programmably configurable to connect different selectable datapath sections in the digital blocks to other different selectable functional elements and to different selectable connectors.

5. The apparatus according to claim 1 wherein:

the system level interconnect is configured to operate a selected one of the connectors as an input pin by coupling the selected connector to an input for one of the functional elements while the integrated circuit is in a first operational state; and

the system level interconnect is further configured to operate the same selected connector as an output pin by coupling the same selected connector to an output for one of the functional elements while the integrated circuit is in a second operational state.

6. The apparatus according to claim 1 wherein the system level interconnect is configured to synchronously multiplex analog signals from different connectors to a same functional element that operates as analog to digital converter.

7. The apparatus according to claim 1 wherein the system level interconnect comprises horizontal channels configured to:

programmably couple to the different functional elements according to the configuration values in the configuration registers or configuration memory; and

programmably couple to the different connectors according to the configuration values in the configuration registers or configuration memory.

8. The apparatus according to claim 7 further comprising:

channel switches that programmably couple the horizontal channels to the different functional elements according to the configuration values; and

segmentation switches that programmably couple the horizontal channels to each other according to the configuration values.

9. The apparatus according to claim 1 further comprising different sets of interface lines coupled to different associated functional elements and other different sets of interface lines coupled to different associated connectors, the interface lines overlapping with multiple different channel lines in associated channels of the system level interconnect and programmably coupled to the different channel lines according to the configuration values.

10. The apparatus according to claim 9 wherein multiple interface lines associated with the same functional elements or associated with the same connectors are shorted together.

11. The apparatus according to claim 10 wherein each of the multiple shorted interface lines are programmably coupled to different channel lines according to the configuration values.

12. The apparatus according to claim 9 further comprising hold cells configured to retain a last state on associated interface lines and further configured to set the associated interface lines to weak predetermined state upon receiving a reset signal.

3. An apparatus, comprising:

different functional elements comprising a micro-controller, analog peripherals and digital peripherals all located in a same integrated circuit;

configuration registers or configuration memory in the integrated circuit to store configuration values loaded by the micro-controller;

different connectors configured to connect the integrated circuit to external signals; and

a system level interconnect located in the integrated circuit to programmably connect together the different functional elements and different connectors according to the configuration values loaded into the configuration registers or configuration memory by the micro-controller

wherein the system level interconnect is programmed according to the configuration values to couple one of the connectors to one of the analog peripherals while the integrated circuit is in a first state and then couple the same connector to one of the digital peripherals when the integrated circuit is in a second different state.

18. The apparatus according to claim 3 further comprising different sets of interface lines coupled to different associated functional elements and other different sets of interface lines coupled to different associated connectors, the interface lines overlapping with multiple different channel lines in associated channels of the system level interconnect and programmably coupled to the different channel lines according to the configuration values.

19. The apparatus according to claim 18 wherein multiple interface lines associated with the same functional elements or associated with the same connectors are shorted together.

20. The apparatus according to claim 19 wherein each of the multiple shorted interface lines are programmably coupled to different channel lines according to the configuration values.

13. An integrated circuit, comprising:

an interconnect configured to programmably couple together different selectable functional elements and different selectable connectors in the integrated circuit according to configuration values that can be programmably changed in real-time while the integrated circuit is in operation;

wherein the interconnect comprises different sets of interface lines coupled to the different associated functional elements or the different associated integrated circuit connectors, the interface lines overlapping and selectively coupled to the different channel lines according to the configuration values.

14. The integrated circuit according to claim 13 wherein the interconnect comprises channels that programmably couple to different functional elements in the integrated circuit and programmably couple to different connectors in the integrated circuit according to the configuration values.

15. The integrated circuit according to claim 14 further comprising segmentation elements that programmably couple together the channels according to the configuration values.

16. The integrated circuit according to claim 14 further comprising an array of universal digital blocks that each include uncommitted programmable logic sections and structural arithmetic logic sections, the interconnect programmably configured to connect different selectable programmable logic sections and different selectable arithmetic logic sections to associated channels in the interconnect.

17. The integrated circuit according to claim 13 wherein multiple different interface lines associated with a same element or same connector are shorted together.