CMOS circuitry with mixed transistor parameters
First Claim
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1. An electronic circuit comprising:
- a first transistor having a source terminal coupled to a first node and a drain terminal coupled to a second node, wherein the first transistor has a first nominal threshold voltage;
a second transistor of the same type as the first transistor, the second transistor having a source terminal coupled to the first node and a drain terminal coupled to the second node, wherein the second transistor has a second nominal threshold voltage;
a third transistor having a drain terminal coupled to the second node and a source terminal coupled to a third node, the third transistor being of a different type than the first and second transistors, wherein the third transistor has a third nominal threshold voltage, and wherein gate terminals of the first and third transistors are coupled together; and
a fourth transistor having a drain terminal coupled to the second node and a source terminal coupled to the third node, the fourth transistor being of the same type as the third transistor, wherein the fourth transistor has a fourth nominal threshold voltage, and wherein gate terminals of the second and fourth transistors are coupled together;
wherein each of the first, second, third, and fourth nominal threshold voltages is different from each of the other ones of the first, second, third, and fourth nominal threshold voltages.
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Abstract
CMOS circuitry having mixed threshold voltages is disclosed. Circuits may be implemented using PMOS transistors, NMOS transistors, or both. For at least one given type of transistor (PMOS or NMOS), a circuit includes at least one transistor configured to switch at a first nominal threshold voltage and at least one transistor configured to switch at a second nominal threshold voltage. The different threshold voltages among a given transistor type are realized by varying the thickness of the transistor gate oxides and/or the channel dopant density, for example.
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Citations
18 Claims
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1. An electronic circuit comprising:
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a first transistor having a source terminal coupled to a first node and a drain terminal coupled to a second node, wherein the first transistor has a first nominal threshold voltage; a second transistor of the same type as the first transistor, the second transistor having a source terminal coupled to the first node and a drain terminal coupled to the second node, wherein the second transistor has a second nominal threshold voltage; a third transistor having a drain terminal coupled to the second node and a source terminal coupled to a third node, the third transistor being of a different type than the first and second transistors, wherein the third transistor has a third nominal threshold voltage, and wherein gate terminals of the first and third transistors are coupled together; and a fourth transistor having a drain terminal coupled to the second node and a source terminal coupled to the third node, the fourth transistor being of the same type as the third transistor, wherein the fourth transistor has a fourth nominal threshold voltage, and wherein gate terminals of the second and fourth transistors are coupled together; wherein each of the first, second, third, and fourth nominal threshold voltages is different from each of the other ones of the first, second, third, and fourth nominal threshold voltages. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A logic gate comprising:
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a plurality of p-type metal oxide semiconductor (PMOS) transistors including a first subset of PMOS transistors having a first PMOS transistor, wherein each PMOS transistor of the first subset of PMOS transistors is configured to activate based on a first gate-source voltage, and a second subset of PMOS transistors including a second PMOS transistor, wherein each PMOS transistor of the second subset of PMOS transistors is configured to activate responsive to a second gate-source voltage different from the first gate-source voltage; and a plurality of n-type metal oxide semiconductor (NMOS) transistors including a first subset of NMOS transistors having a first NMOS transistor, wherein each NMOS transistor of the first subset of NMOS transistors is configured to activate based on a third gate-source voltage, and a second subset of NMOS transistors including a second NMOS transistor, wherein each NMOS transistor of the second subset of NMOS transistors is configured to activate responsive to a fourth gate-source voltage different from the third gate-source voltage; wherein a gate terminal of each of the plurality of PMOS transistors is coupled to a corresponding gate terminal of a corresponding one of the plurality of NMOS transistors. - View Dependent Claims (10, 11, 12)
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13. An integrated circuit comprising:
a plurality of logic gates, wherein the power switch circuit and each of the plurality of logic gates includes a first plurality of p-type metal oxide semiconductor (PMOS) transistors, a second plurality of PMOS transistors, a first plurality of n-type metal oxide semiconductor (NMOS) transistors, and a second plurality of NMOS transistors, wherein; each of the PMOS transistors of the first plurality of PMOS transistors is configured to become active responsive to a gate-source voltage less than a first nominal threshold voltage; each of the PMOS transistors of the second plurality of PMOS transistors is configured to become active responsive to a gate-source voltage less than a second nominal threshold voltage; each of the NMOS transistors of the first plurality of NMOS transistors is configured to become active responsive to a gate-source voltage greater than a third nominal threshold voltage; each of the NMOS transistors of the second plurality of NMOS transistors is configured to become active responsive to a gate-source voltage greater than a fourth nominal threshold voltage; wherein a gate terminal of each of the first plurality of PMOS transistors is coupled to a gate terminal of a corresponding one of the first plurality of NMOS transistors; and wherein a gate terminal of each of the second plurality of PMOS transistors is coupled to a gate terminal of a corresponding one of the second plurality of NMOS transistors. - View Dependent Claims (14, 15, 16, 17, 18)
Specification