Display controller, graphics processor, rendering processing apparatus, and rendering control method

• US 8,026,919 B2
• Filed: 11/30/2006
• Issued: 09/27/2011
• Est. Priority Date: 04/19/2006
• Status: Active Grant

• Current Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Original Assignee: Sony Computer Entertainment Incorporated (Sony Group Corp.)
• Inventors: Aoki, Sachiyo
• Primary Examiner(s): Washburn; Daniel
• Application Number:
  US12/297,546
• Publication Number:
  US 20090225088A1
• Time in Patent Office: 1,762 Days
• Field of Search: 345/501, 345/503, 345/536, 345/539
• US Class Current: 345/501
• CPC Class Codes: G09G 2340/0435 Change or adaptation of the frame rate of the video stream
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers
• CPC Class Codes: H04N 5/46 for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27
• CPC Class Codes: H04N 7/012 Conversion between an interlaced and a progressive signal for graphics images G09G2310/0229
• CPC Class Codes: H04N 7/0132 the field or frame frequency of the incoming video signal being multiplied by a positive integer, e.g. for flicker reduction

Abstract

A rendering processing unit of a graphics processor selects a buffer in a frame buffer in which to write rendering data by switching between multiple buffers in the frame buffer and writes rendering data accordingly; a display controller selects a buffer in the frame buffer from which to read rendering data by switching between a plurality of buffers in the frame buffer according to a sequence, and supplies the rendering data read by scanning the frame buffer to a display; a switching signal generating unit generates a buffer switching signal for directing the display controller to switch the buffer in the frame buffer from which to read at a frequency different from a vertical synchronization frequency of the display assumed by the graphics processor.

Claims

1. A graphics processor operative to supply a buffer switching signal for timing of switching between a plurality of frame buffers, each of which is adapted to hold a frame of rendering data, to a display controller which switchably selects one of the frame buffers according to a sequence, and supplies the rendering data read by scanning the selected frame buffer to a display,

wherein the graphics processor determines whether a vertical synchronization frequency which the graphics processor assumes when generating the rendering data frame by frame matches an actual vertical synchronization frequency of the display, and when the frequencies do not match, generates the buffer switching signal at the assumed vertical synchronization frequency, and when the frequencies match, generates the buffer switching signal at the actual vertical synchronization frequency of the display, and

wherein the selected frame buffer from which the rendering data is to be read is switched to another frame buffer when the buffer switching signal is received such that the display switches the buffers at the assumed vertical synchronization frequency and a time point of the buffer switch is determined independently from a time of occurrence of a vertical synchronization of the display when the frequencies do not match.

2. A rendering processing apparatus comprising:

a plurality of frame buffers each of which is operative to hold a frame of rendering data;

a rendering processing unit operative to switchably select a frame buffer in which to write rendering data from the plurality of frame buffers according to a sequence, and to generate the rendering data in the selected frame buffer in which to write;

a display controller operative to switchably select a frame buffer from which to read rendering data from the plurality of buffers according to a sequence, and to supply to a display the rendering data read by scanning the selected frame buffer from which to read; and

a switching signal generating unit operative to generate a buffer switching signal directing the display controller to switch the frame buffer from which to read, wherein

the switching signal generating unit determines whether a frequency of a dummy vertical synchronization signal that is independent of a synchronization signal of the display matches an actual vertical synchronization frequency of the display, and when the frequencies do not match, generates the buffer switching signal at the timing of the dummy vertical synchronization signal, and when the frequencies match, generates the buffer switching signal at the timing of the actual vertical synchronization frequency of the display, and

wherein the selected frame buffer from which the rendering data is to be read is switched to another frame buffer when the buffer switching signal is received such that the display switches the buffers at the assumed vertical synchronization frequency and a time point of the buffer switch is determined independently from a time of occurrence of a vertical synchronization of the display when the frequencies do not match.

3. The rendering processing apparatus according to claim 2, wherein the buffer switching signal is also used to direct the rendering processing unit to switch the frame buffer in which to write.

4. The rendering processing apparatus according to claim 2, wherein the switching signal generating unit generates the buffer switching signal at a frequency of a dummy synchronization signal generated at a vertical synchronization frequency which the rendering processing unit assumes when generating rendering data frame by frame.

5. The rendering processing apparatus according to claim 2, wherein the display controller produces one frame for the display by combining rendering data that is scanned from at least two of the plurality of buffers.

6. A rendering processing apparatus comprising:

a plurality of frame buffers each of which is operative to hold a frame of rendering data;

a rendering processing unit operative to switchably select a frame buffer in which to write the rendering data according to a sequence, and to generate the rendering data in the selected frame buffer in which to write;

a display controller operative to switchably select a frame buffer from which to read rendering data according to a sequence, and to supply to a display the rendering data read by scanning the selected frame buffer from which to read; and

a switching signal generating unit operative to generate a buffer switching signal directing the display controller to switch the frame buffer from which to read, wherein

the switching signal generating unit determines whether a vertical synchronization frequency which the rendering processing unit assumes when generating the rendering data frame by frame matches an actual vertical synchronization frequency of the display, and when the frequencies do not match, generates the buffer switching signal at the assumed vertical synchronization frequency, and when the frequencies match, generates the buffer switching signal at the actual vertical synchronization frequency of the display, and

wherein the selected frame buffer from which the rendering data is to be read is switched to another frame buffer when the buffer switching signal is received such that the display switches the buffers at the assumed vertical synchronization frequency and a time point of the buffer switch is determined independently from a time of occurrence of a vertical synchronization of the display when the frequencies do not match.

7. A rendering control method adapted for a display controller, comprising:

switchably selecting one of a plurality of frame buffers, each of which is adapted to hold a frame of rendering data according to a sequence;

supplying the rendering data read by scanning the selected frame buffer to a display;

controlling the timing of switching the frame buffer scanned by the display controller in accordance with a dummy vertical synchronization signal that is independent of a synchronization signal of the display;

determining whether a frequency of the dummy vertical synchronization signal matches a frequency of the synchronization signal of the display;

setting, when the frequencies do not match, the timing of switching to the timing of the dummy vertical synchronization signal wherein a time point of the switching is determined independently from a time of occurrence of a vertical synchronization of the display;

setting, when the frequencies match, the timing of switching to the timing of the synchronization signal of the display, and

switching the selected frame buffer from which the rendering data is to be read to another frame buffer when the buffer switching signal is received such that the display switches the buffers at the assumed vertical synchronization frequency when the frequencies do not match.