Processor instruction cache with dual-read modes

• US 8,027,218 B2
• Filed: 04/02/2008
• Issued: 09/27/2011
• Est. Priority Date: 10/13/2006
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Sheu, Jason, Tjeng, Jensen, Sutardja, Sehat, Chen, Hong-Yi, Su, Jason T.
• Primary Examiner(s): Nguyen; Tuan T
• Assistant Examiner(s): REIDLINGER, RONALD LANCE
• Application Number:
  US12/061,296
• Publication Number:
  US 20080189518A1
• Time in Patent Office: 1,273 Days
• Field of Search: 365/154, 365/156, 365/230.06, 365/203, 365/190, 712/207, 712/225, 712/E9.033
• US Class Current: 365/230.06
• CPC Class Codes: G06F 12/0882 Page mode
• CPC Class Codes: G06F 9/30054 Unconditional branch instructions
• CPC Class Codes: G06F 9/30058 Conditional branch instructions
• CPC Class Codes: G06F 9/3804 for branches, e.g. hedging, branch folding
• CPC Class Codes: G06F 9/3844 using dynamic branch prediction, e.g. using branch history tables
• CPC Class Codes: G11C 2207/2245 Memory devices with an internal cache buffer
• CPC Class Codes: G11C 2207/2281 Timing of a read operation sense amplifier timing G11C7/06, G11C7/08
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A processor includes a cache memory that has an array, word lines, and bit lines. A control module accesses cells of the array during access cycles to access instructions stored in the cache memory. The control module performs one of a first discrete read and a first sequential read to access instructions in a first set of cells of the array that are connected to a first word line and selectively performs one of a second discrete read and a second sequential read based on a branch instruction to access instructions in a second set of cells of the array that are connected to a second word line. The second word line is different than the first word line.

Claims

1. A processor comprising:

a cache memory that comprises;

an array;

word lines;

bit lines;

a control module that accesses cells of said array during access cycles to access instructions stored in said cache memory; and

a row decoder,

wherein said control module selectively performs one of a first sequential read and a first discrete read to access instructions in a first set of cells of said array that are connected to a first word line and that selectively performs one of a second sequential read and a second discrete read based on a first branch instruction to access instructions in a second set of cells of said array that are connected to a second word line, and

wherein said control module generates a word line signal via said row decoder to access said first set of cells,

wherein said word line signal defines an extended period to increase bit line separation,

wherein said extended period is based on a predetermined number of read cycles, and

wherein said second word line is different than said first word line.

2. The processor of claim 1 wherein said control module, when performing said first sequential read, enables said first word line of said cache memory to access a first cell in said first word line, disables said first word line, and maintains said first word line in a disabled state when accessing a second cell in said first word line.

3. The processor of claim 1 wherein said control module, when performing said first sequential read, generates a first word line pulse associated with said first word line for a first access cycle of said bit lines and selectively refrains from generating a second word line pulse for said first word line for a second access cycle of said bit lines.

4. The processor of claim 1 wherein said control module determines bit line separation based on a number of said access cycles to be performed along a first word line, and

wherein said control module precharges said bit lines connected to said first word line to provide said bit line separation when accessing said first set of cells.

5. The processor of claim 4 wherein said control module precharges a set of said bit lines connected to said first word line to provide said bit line separation when accessing a first set of cells of said array, and

wherein said control module selectively refrains from precharging at least one of said set of said bit lines when accessing a second set of cells of said array based on connections between said second set of cells and said first word line.

6. The processor of claim 5 wherein said control module refrains from precharging said at least one of said set of said bit lines when said second set of cells is connected to said first word line.

7. The processor of claim 5 wherein said control module precharges said at least one of said set of bit lines when said second set of cells is connected to a word line other than said first word line.

8. The processor of claim 1 wherein said control module adjusts precharge timing of said bit lines based on a rate of a clock signal.

9. The processor of claim 1 wherein said control module delays precharging of said bit lines when a rate of a clock signal is less than a predetermined rate.

10. The processor of claim 1 wherein said control module selectively operates in a discrete read mode and a sequential read mode.

11. The processor of claim 1 wherein said control module generates a sequential read signal to enable a sequential read mode and generates said word line signal based on said sequential read signal.

12. The processor of claim 1 wherein said control module generates a sequential read signal to enable a sequential read mode and precharges said bit lines based on said sequential read signal.

13. The processor of claim 1 wherein said control module, when in a discrete mode, performs row address decoding, word line enablement, and bit line precharging for each access of each of said cells.

14. The processor of claim 1 wherein said control module, when accessing cells in a first mode, precharges said bit lines and performs row address decoding for each read cycle, and

wherein said control module, when accessing cells in a second mode, precharges said bit lines, performs row address decoding for a first read cycle, does not precharge said bit lines, and does not perform row address decoding for a second read cycle.

15. The processor of claim 1 further comprising a column decoder that selects cells of said array via a column select signal, wherein said control module generates a latch signal to latch bit information in said selected cells based on said column select signal.

16. The processor of claim 1 further comprising an amplification module that detects and amplifies bit information in said first and second set of cells.

17. The processor of claim 1 wherein said extended period increases bit line separation time and sets said bit line separation at a predetermined voltage.

18. The processor of claim 1 further comprising a column decoder, wherein said control module generates bit line signals via said column decoder to access said first set of cells.

19. The processor of claim 1 further comprising a sense-amplifier that has a plurality of common lines and that receives a precharge signal to precharge said common lines before latching bit information in said first and second set of cells.

20. The processor of claim 1 wherein said control module precharges said bit lines based on a precharge flag that indicates when a precharge has been performed.

21. The processor of claim 1 wherein said control module precharges said bit lines based on timing of a previous precharge of said bit lines.

22. The processor of claim 1 wherein said control module, when performing said second sequential read, enables said second word line of said cache memory to access a cell in said second word line, disables said second word line, and maintains said second word line in a disabled state when accessing another cell in said second word line.

23. The processor of claim 1 wherein said control module performs in a discrete read mode based on said first branch instruction.

24. The processor of claim 1 wherein said processor pre-fetches and decodes subsequent instructions in a pipeline and further comprising a branch prediction module that predicts whether one of said subsequent instructions that is a second branch instruction is likely to be taken.

25. The processor of claim 24 wherein said branch prediction module selectively performs one of a discrete read and a sequential read on said branch instruction based on said prediction and on whether said branch instruction involves multiple reads along a same word line.

26. The processor of claim 25 wherein said branch prediction module includes a branch history module that outputs branch prediction data based on an address of said second branch instruction and wherein said branch prediction module bases said prediction on said branch prediction data.

27. A method comprising:

providing a cache memory that comprises;

an array of cells;

word lines;

bit lines; and

a row decoder;

accessing cells of said array during access cycles to access instructions stored in said cache memory;

performing one of a first discrete read and a first sequential read to access instructions in a first set of cells of said array that are connected to a first word line; and

selectively performing one of a second discrete read and a second sequential read based on a first branch instruction to access instructions in a second set of cells of said array that are connected to a second word line; and

generating a word line signal via said row decoder to access said first set of cells,

wherein said word line signal defines an extended period to increase said bit line separation,

wherein said extended period increases bit line separation time and sets said bit line separation at a predetermined voltage, and

wherein said second word line is different than said first word line.

28. The method of claim 27 further comprising, when performing said first sequential read, enabling said first word line of said cache memory to access a first cell in said first word line, disabling said first word line, and maintaining said first word line in a disabled state when accessing a second cell in said first word line.

29. The method of claim 27 further comprising, when performing said first sequential read, generates a first word line pulse associated with said first word line for a first access cycle of said bit lines and selectively refrains from generating a second word line pulse for said first word line for a second access cycle of said bit lines.

30. The method of claim 27 further comprising:

determining bit line separation based on a number of said access cycles to be performed along a first word line; and

precharging said bit lines connected to said first word line to provide said bit line separation when accessing said first set of cells.

31. The method of claim 30 further comprising:

precharging a set of said bit lines connected to said first word line to provide said bit line separation when accessing a first set of cells of said array; and

selectively refraining from precharging at least one of said set of said bit lines when accessing a second set of cells of said array based on connections between said second set of cells and said first word line.

32. The method of claim 31 further comprising refraining from precharging said at least one of said set of said bit lines when said second set of cells is connected to said first word line.

33. The method of claim 31 further comprising precharging said at least one of said set of bit lines when said second set of cells is connected to a word line other than said first word line.

34. The method of claim 27 further comprising adjusting precharge timing of said bit lines based on a rate of a clock signal.

35. The method of claim 27 further comprising delaying precharging of said bit lines when a rate of a clock signal is less than a predetermined rate.

36. The method of claim 27 further comprising selectively operating in a discrete read mode and a sequential read mode.

37. The method of claim 27 further comprising generating a sequential read signal to enable a sequential read mode and generating said word line signal based on said sequential read signal.

38. The method of claim 27 further comprising generating a sequential read signal to enable a sequential read mode and precharging said bit lines based on said sequential read signal.

39. The method of claim 27 further comprising, when in a discrete mode, performing row address decoding, word line enablement, and bit line precharging for each access of each of said cells.

40. The method of claim 27 further comprising:

when accessing cells in a first mode, precharging said bit lines and performing row address decoding for each read cycle; and

when accessing cells in a second mode, precharging said bit lines, performing row address decoding for a first read cycle, refraining from precharging said bit lines, and refraining from performing row address decoding for a second read cycle.

41. The method of claim 27 further comprising:

selecting cells of said array via a column select signal, and

generating a latch signal to latch bit information in said selected cells based on said column select signal.

42. The method of claim 27 further comprising detecting and amplifying bit information in said first and second set of cells.

43. The method of claim 27 wherein said word line signal defines an extended period to increase said bit line separation.

44. The method of claim 27 further comprising generating bit line signals via said column decoder to access said first set of cells.

45. The method of claim 27 further comprising receiving a precharge signal to precharge common lines of a sense-amplifier before latching bit information in said first and second set of cells.

46. The method of claim 27 further comprising precharging said bit lines based on a precharge flag that indicates when a precharge has been performed.

47. The method of claim 27 further comprising precharging said bit lines based on timing of a previous precharge of said bit lines.

48. The method of claim 27 further comprising, when performing said second sequential read, enabling said second word line of said cache memory to access a cell in said second word line, disabling said second word line, and maintaining said second word line in a disabled state when accessing another cell in said second word line.

49. The method of claim 27 further comprising performing in a discrete read mode based on said first branch instruction.

50. The method of claim 27 further comprising:

pre-fetching and decoding subsequent instructions in a pipeline;

predicting whether one of said subsequent instructions that is a second branch instruction is likely to be taken.

51. The method of claim 50 further comprising:

selectively performing one of a discrete read and a sequential read on said branch instruction based on said prediction and on whether said branch instruction involves multiple reads along a same word line.

52. The method of claim 51 further comprising:

generating branch prediction data based on an address of said second branch instruction; and

basing said prediction on said branch prediction data.