Wireless radio frequency technique design and method for testing of integrated circuits and wafers

• US 8,028,208 B2
• Filed: 02/26/2007
• Issued: 09/27/2011
• Est. Priority Date: 05/15/2000
• Status: Expired due to Fees

• Current Assignee: Scanimetrics, Inc.
• Original Assignee: Scanimetrics, Inc.
• Inventors: Moore, Brian
• Primary Examiner(s): Chung, Phung M
• Application Number:
  US11/678,924
• Publication Number:
  US 20070162801A1
• Time in Patent Office: 1,674 Days
• Field of Search: 714/724, 714/732, 714/37, 714/36, 714/48, 324/765, 324/763, 324/754
• US Class Current: 714/724
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: G01R 31/303 of integrated circuits G01R31/305 - G01R31/315 take precedence
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

Various embodiments are described herein for an apparatus and method for the wireless testing of Integrated Circuits and wafers. In one embodiment, the apparatus comprises a test unit external from the wafer and at least one test circuit that is fabricated on the wafer that contains the Integrated Circuit. The test unit transmits an RF signal to power the test circuit. The test circuit, comprising configurable circuitry, performs a series of parametric tests at the normal operating frequency of the Integrated Circuit and transmits the test results to the test unit for analysis.

Claims

1. Apparatus for testing an integrated circuit on a wafer, the apparatus comprising:

a) a test circuit formed on the wafer with the integrated circuit, the test circuit comprising;

i) configurable circuitry including a plurality of selectable sub-circuits;

ii) a control circuit configured to selectively enable at least one of the sub-circuits, and b) a test unit separate from the wafer, the test unit wirelessly linked to the test circuit to transmit a signal to activate the test circuit, wherein the test circuit, when activated by the test unit, is configured to conduct a separate test of the integrated circuit for each sub-circuit selectively enabled by the control circuit and generate a test result signal for analysis by the test unit.

2. The apparatus of claim 1, wherein the integrated circuit comprises a plurality of sub-circuits or a plurality of selectable sub-circuits or both in combination.

3. The apparatus of claim 1, wherein the configurable circuitry comprises at least one transmitter, at least one receiver or at least one transmitter and at least one receiver.

4. The apparatus of claim 1, wherein each test conducted by the test circuit is at least one of a parametric test and a functional test.

5. The apparatus of claim 1, wherein each of the sub-circuits when coupled to the configurable circuitry changes the test result signal.

6. The apparatus of claim 1, wherein the control circuit comprises a sequencer to selectively enable the sub-circuits in the configurable circuitry to produce a test result or a series of test results.

7. The apparatus of claim 1, wherein the signal produced by the test unit is a power signal sufficient to energize at least one of the test circuit and the integrated circuit.

8. The apparatus of claim 7, wherein the power signal produced by the test unit is a RF power signal.

9. The apparatus of claim 1, wherein the test circuit is formed on the wafer with at least two metallization layers of the integrated circuit.

10. The apparatus of claim 1, wherein the test circuit is formed on the wafer with at least one metallization layer and one polysilicon layer of the integrated circuit.

11. The apparatus of claim 1, wherein the test circuit further comprises a transmitter circuit to transmit the test result signal from the test circuit to the test unit.

12. The apparatus of claim 11, wherein the test unit comprises at least one receiver circuit to receive the test result signal from the test circuit or a plurality of test result signals from a plurality of test circuits formed on the wafer.

13. The apparatus of claim 12, wherein the test unit further comprises a circuit configured to analyze and/or display at least one test result signal.

14. The apparatus of claim 13, wherein the analyzing circuit is configured to calculate a value from the at least one test result signal.

15. The apparatus of claim 11, wherein the transmitter circuit comprises a coupler which couples the at least one output of the sub-circuits to an antenna for transmission of the test result signal to the test unit.

16. The apparatus of claim 15, wherein the coupler is configured to capacitively couple the test result signal to the antenna.

17. The apparatus of claim 15, wherein the coupler is configured to modulate the impedance of the antenna to transmit the test result signal to the test unit.

18. The apparatus of claim 15, wherein the coupler is further configured to modulate at least one output of the sub-circuits.

19. The apparatus of claim 15, wherein the transmitter circuit further comprises a synchronization element to couple the at least one output of the sub-circuits to the coupler.

20. The apparatus of claim 1, wherein the test circuit is configured to produce the test result signal from the output of the configurable circuitry.

21. The apparatus of claim 1, wherein the test circuit further comprises at least one antenna.

22. The apparatus of claim 21, wherein the at least one antenna is adapted to perform at least one of:

receiving the signal from the test unit, and transmitting at least one additional signal to the test unit.

23. The apparatus of claim 22, wherein the test circuit further comprises a power supply circuit adapted to provide power to at least one of the test circuit and the integrated circuit.

24. The apparatus of claim 23, wherein the power supply circuit is coupled to the at least one antenna.

25. The apparatus of claim 23, wherein the power supply circuit comprises a voltage rectifier coupled to the antenna, a voltage regulator coupled to the voltage rectifier and an energy storage element coupled to the voltage regulator, wherein the power supply circuit is adapted to provide a plurality of voltage levels to at least one of the test circuit and the integrated circuit.

26. The apparatus of claim 21, wherein the integrated circuit comprises at least one antenna for transmitting signals between the integrated circuit and the test circuit or the test unit.

27. The apparatus of claim 26, wherein the at least one antenna is external to at least one of the integrated circuit and the test circuit.

28. The apparatus of claim 26, wherein the at least one antenna is a monopole antenna.

29. The apparatus of claim 26, wherein the at least one antenna is a dipole antenna.

30. The apparatus of claim 26, wherein the at least one antenna is a patch antenna.

31. The apparatus of claim 26, wherein the at least one antenna is a spiral antenna.

32. The apparatus of claim 21, wherein the at least one antenna is located in a die that contains the test circuit.

33. The apparatus of claim 32, wherein the test unit comprises at least one antenna.

34. The apparatus of claim 33, wherein the at least one antenna of the test unit has a similar size and geometry to the at least one antenna of the test circuit for transmission of signals therebetween.

35. The apparatus of claim 33, wherein the test unit comprises a logic means in a circuit that includes the at least one antenna.

36. The apparatus of claim 33, wherein the at least one antenna of the test circuit is optimized to provide close coupling with the at least one antenna of the test unit.

37. The apparatus of claim 1, wherein there is a plurality of test circuits on the wafer and the test unit is configured to test each test circuit sequentially.

38. The apparatus of claim 1, wherein there is a plurality of test circuits on the wafer and the test unit is configured to test the plurality of test circuits in parallel.

39. The apparatus of claim 1, wherein the test circuit is formed adjacent to a die containing the integrated circuit.

40. The apparatus of claim 1, wherein the test circuit is formed on a die that contains the integrated circuit.

41. The apparatus of claim 1, wherein the test circuit is formed on a large percentage of dies on the wafer.

42. The apparatus of claim 1, wherein the test circuit is formed on dies near the edge of the wafer.

43. The apparatus of claim 1, wherein the test unit comprises circuitry configured to test a plurality of test circuits in at least one of a simultaneous manner, a sequential manner, and a sequential activation of combinations of the plurality of test circuits.

44. The apparatus of claim 1, wherein the test unit has at least one antenna for transmission of signals between the test unit and the test circuit, the at least one antenna having a size and a geometry selected so as to optimize transmission of signals between the at least one antenna and an antenna of the test circuit.

45. The apparatus of claim 44, wherein the test circuit and the antenna of the test unit are situated in close proximity with each other so as to maximize the strength of signals received transmitted there between.

46. The apparatus of claim 1, wherein electronics of the test unit are manufactured on a scale that is similar to electronics of the test circuit.

47. The apparatus of claim 46, wherein the test unit is manufactured using the same or similar technology and methodology as that used to manufacture the test circuit.

48. The apparatus of claim 1, wherein the location of the test circuit is moveable relative to the integrated circuit.

49. A method of testing an integrated circuit on a wafer using a test circuit formed on the wafer with the integrated circuit, the method comprising:

(a) employing a test circuit comprising configurable circuitry including a plurality of sub-circuits, and a control circuit to selectively enable at least one of the sub-circuits to vary the configuration of the configurable circuitry;

(b) activating the test circuit;

(c) selectively enabling the sub-circuits;

(d) producing a test result signal in response to each sub-circuit selectively enabled by the control circuit; and

,

(e) analyzing the test result signal.

50. The method of claim 49, wherein the configurable circuitry comprises at least one transmitter, at least one receiver or at least one transmitter and at least one receiver.

51. The method of claim 49, wherein each test conducted by the test circuit is at least one of a parametric test and a functional test.

52. The method of claim 49, wherein the method further comprises:

(f) calculating a value for a test result.

53. The method of claim 49, wherein step (d) further comprises the steps of:

(i) coupling the test result signal to an antenna within the test circuit through a coupler in the test circuit; and

, (ii) modulating the coupler to transmit the test result signal to a test unit to allow the test unit to synchronize to the test result signal and analyze the test result signal.

54. The method of claim 53, wherein step (ii) further comprises providing a synchronization element to modulate the coupler.

55. The method of claim 49, wherein the control circuit comprises a sequencer.

56. The method of claim 49, wherein there are a plurality of test circuits on the wafer and the method further comprises testing each test circuit sequentially.

57. The method of claim 49, wherein there are a plurality of test circuits on the wafer and the method further comprises testing each test circuit in parallel.

58. The method of claim 49, wherein the test circuit, when activated, is configured to conduct a separate test of the integrated circuit for each sub-circuit selected by the control circuit.

59. The method of claim 49, wherein the method further comprises employing a test unit having circuitry for activating a plurality of test circuits in at least one of a simultaneous manner, a sequential manner, and a sequential activation of combinations of the plurality of test circuits.

60. The method of claim 49, wherein the method further comprises encoding a sequence number within the test result signal, the sequence number indicating at least one of a test circuit location and an operation tested at the test circuit location.

61. The method of claim 49, wherein the method further comprises encoding a sequence number within the test result signal, the sequence number indicating at least one of a test circuit location and a function tested at the test circuit location.

62. The method of claim 49, wherein the test circuit comprises a sequencer and the method further comprises using the sequencer to test at least one sub-circuit of the integrated circuit that is located remotely from the test circuit.

63. The method of claim 49, wherein the method further comprises using the configurable circuitry of the test circuit to test at least one integrated circuit on the wafer.