Multiple-core processor supporting multiple instruction set architectures

• US 8,028,290 B2
• Filed: 08/30/2006
• Issued: 09/27/2011
• Est. Priority Date: 08/30/2006
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: International Business Machines Corporation
• Inventors: Heller, Thomas J. Jr., Ignatowski, Michael, Rymarczyk, James Walter
• Primary Examiner(s): Chan; Eddie
• Assistant Examiner(s): GIROUX, GEORGE
• Application Number:
  US11/468,547
• Publication Number:
  US 20080059769A1
• Time in Patent Office: 1,854 Days
• Field of Search: 712/203, 712/32, 718/104
• US Class Current: 718/104
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 15/7842 on one IC chip (single chip microcontrollers)
• CPC Class Codes: G06F 2209/507 Low-level
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/45533 Hypervisors; Virtual machine monitors
• CPC Class Codes: G06F 9/5077 Logical partitioning of resources; Management or configuration of virtualized resources specific details on emulation or internal functioning of virtual machines G06F9/455
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Multiple instruction set architectures are supported in a system that provides a power-efficient and flexible platform for virtual machine environments requiring multiple support for multiple instruction set architectures (ISAs). A processor includes multiple cores having disparate native ISAs and that may be selectively enabled for operation, so that power is conserved when support for a particular ISA is not required of the processor. A hypervisor controls operation of the cores, locates a core and enables it if necessary when a request to instantiate a virtual machine having a specified ISA is received. The ISA may be specified by a particular operating system and/or application program requirements.

Claims

1. A method of managing operation of a processing system supporting multiple instruction sets, wherein said processing system supports execution of multiple operating system images within multiple virtual machines, said method comprising:

receiving a request to instantiate a virtual machine having a specified instruction set, wherein the instruction set is an instruction set required for execution of the virtual machine and is specified in conjunction with the request from among the multiple instruction sets supported by the processing system;

determining an availability status of a given core that supports the specified instruction set within a processor having multiple cores, at least one core supporting said specified instruction set and at least one other core not supporting said specified instruction set and supporting another instruction set, wherein only one of the multiple cores is selectable for operation at any given time, and wherein power is supplied to only a selected one of the multiple cores that is selected for operation;

in response to determining that said given core is available, selecting the given core for execution of the virtual machine from among the multiple cores by applying a power supply voltage to the given core and instantiating said virtual machine on said core; and

further comprising in response to determining that said given core is not available, failing instantiation of said virtual machine.

2. The method of claim 1, further comprising:

determining whether or not said given core is disabled; and

enabling said given core in response to determining that said given core is disabled.

3. The method of claim 1, wherein the specified instruction set and the another instruction set implement instruction sets are incompatible with each other.

4. The method of claim 1, further comprising:

receiving a request to execute a particular operating system program requiring said specified instruction set; and

generating the request to instantiate the virtual machine having the specified instruction set in response to receiving the request to execute the particular operating system program.

5. The method of claim 1, further comprising:

receiving a request to execute a particular application program;

generating the request to instantiate the virtual machine having the specified instruction set in response to receiving the request to execute the particular application program, wherein the instantiating the virtual machine executes a particular operating system program required for execution of the particular application program; and

executing the application program within the virtual machine.

6. A method of managing operation of a processing system supporting multiple incompatible instruction sets, wherein said processing system supports execution of multiple operating system images within multiple virtual machines, said method comprising:

receiving a request to execute a particular application program;

generating a request to instantiate a virtual machine having a specified instruction set from among the multiple instruction sets supported by the processing system and a specified operating system program in response to receiving the request to execute the particular application program, wherein the specified operating system program is an operating system program required for execution of the particular application program and the specified instruction set is an instruction set required for execution of the specified operating system program;

determining an availability status of a given core that supports the specified instruction set within a processor having multiple cores, at least one core supporting said specified instruction set and at least one other core not supporting said specified instruction set and supporting another instruction set incompatible with the specified instruction set, and wherein only one of the multiple cores is selectable for operation at any given time, and wherein power is supplied to only a selected one of the multiple cores that is selected for operation;

in response to determining that said given core is available, selecting the given core for execution of the virtual machine from among the multiple cores by applying a power supply voltage to the given core and instantiating said virtual machine on said core and executing the particular operating system;

in response to determining that said given core is not available, failing instantiation of said virtual machine; and

executing the application program within the virtual machine.

7. A processing system comprising:

a memory for storing program instructions and data; and

a processor for executing said program instructions, said program instructions including multiple operating systems executing within multiple virtual machines, wherein said program instructions further comprise hypervisor program instructions for managing said virtual machines, and wherein said hypervisor program instructions comprise program instructions for

receiving a request to instantiate a virtual machine having a specified instruction set, wherein the instruction set is an instruction set required for execution of the virtual machine and is specified in conjunction with the request from among the multiple instruction sets supported by the processing system;

determining an availability status of a given core that supports the specified instruction set within a processor having multiple cores, at least one core supporting said specified instruction set and at least one other core not supporting said specified instruction set and supporting another instruction set that is incompatible with the specified instruction set, wherein only one of the multiple cores is selectable for operation at any given time, and wherein power is supplied to only a selected one of the multiple cores that is selected for operation;

selecting the given core for execution of the virtual machine from among the multiple cores by applying a power supply voltage to the given core and instantiating said virtual machine on said core in response to determining that said given core is available; and

failing instantiation of said virtual machine in response to determining that said given core is not available.

8. The processing system of claim 7, further comprising program instructions for:

determining whether or not said given core is disabled; and

enabling said given core in response to determining that said given core is disabled.

9. The processing system of claim 8, wherein said program instructions for enabling enable only one of said multiple cores and disable any other active cores in response to determining that said given core is disabled.