Method of fabricating nonvolatile memory device

• US 8,030,129 B2
• Filed: 12/21/2009
• Issued: 10/04/2011
• Est. Priority Date: 12/24/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Jae-Hyun, Oh, Jae-Hee, Jeong, Ji-Hyun
• Primary Examiner(s): Wilczewski; Mary
• Assistant Examiner(s): Thomas; Toniae M
• Application Number:
  US12/655,047
• Publication Number:
  US 20100159638A1
• Time in Patent Office: 652 Days
• Field of Search: 438/102, 438/637, 257/5, 257/E45.002, 257/E21.068, 257/E21.233, 257/E27.002, 257/E27.004, 257/E47.001, 216/39
• US Class Current: 438/102
• CPC Class Codes: H10B 63/00 Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

Abstract

A method of manufacturing a nonvolatile memory device including forming on a lower insulating layer a first sacrificial pattern having first openings extending in a first direction, forming a second sacrificial pattern having second openings extending in a second direction on the lower insulating layer and the first sacrificial pattern wherein the second openings intersect the first openings, etching the lower insulating layer using the first and second sacrificial patterns to form a lower insulating pattern having contact holes defined by a region where the first and second openings intersect each other, forming a bottom electrode in the contact holes, and forming a variable resistance pattern on the lower insulating pattern so that a portion of the variable resistance pattern connects to a top surface of the bottom electrode.

Claims

1. A method of manufacturing a nonvolatile memory device comprising:

forming a first sacrificial pattern having first openings extending in a first direction on a lower insulating layer;

forming a second sacrificial pattern having second openings extending in a second direction on the lower insulating layer and the first sacrificial pattern, wherein the second openings intersect the first openings;

etching the lower insulating layer using the first and second sacrificial patterns as a mask to form a lower insulating pattern having contact holes defined by a region where the first and second openings intersect each other;

forming a bottom electrode in the contact holes; and

forming a variable resistance pattern on the lower insulating pattern so that a portion of the variable resistance pattern connects to a top surface of the bottom electrode.

2. The method of claim 1, further comprising forming a vertical cell diode within the contact hole, wherein the bottom electrode is formed on the vertical cell diode.

3. The method of claim 2, wherein the forming of the bottom electrode includes conformally forming a conductive layer on the vertical cell diode and along sidewalls of the contact hole, forming a first internal insulating layer on the conductive layer to fill up the contact hole, and removing the conductive layer formed along portions of the sidewalls of the contact hole to form the bottom electrode.

4. The method of claim 3, further comprising forming a second internal insulating layer on the bottom electrode to fill the contact hole.

5. The method of claim 3, wherein the contact hole has a quadrilateral shape including opposite first and second sidewalls and opposite third and fourth sidewalls adjacent to the first sidewall, and, in the removing of the conductive layer formed along portions of the sidewalls of the contact hole, the conductive layer formed along the first sidewall and portions of the third and fourth sidewalls are etched from a top surface of the contact hole.

6. The method of claim 2, wherein the bottom electrode includes a base and a sidewall formed along edges of the base,

further comprising forming an internal insulating layer on the bottom electrode to fill the contact hole and forming an upper insulating pattern on the lower insulating pattern to cover a portion of a top surface of the sidewall.

7. The method of claim 1, further comprising forming bit lines extending in the second direction on the variable resistance pattern, wherein the contact hole has a width extending along the first direction and a length extending along the second direction and the width is greater than the length.

8. The method of claim 7, wherein the variable resistance pattern extends along the second direction and the variable resistance pattern has a width less than the width of the contact hole.

9. The method of claim 1, wherein the variable resistance pattern includes a phase change material.

10. A method of manufacturing a nonvolatile memory device comprising:

forming a first sacrificial pattern having first openings extending in a first direction on a lower insulating layer;

forming a second sacrificial pattern having second openings extending in a second direction on the lower insulating layer and the first sacrificial pattern, wherein the second openings intersect the first openings;

etching the lower insulating layer using the first and second sacrificial patterns as a mask to form a lower insulating pattern having contact holes defined by a region where the first and second openings intersect each other;

forming a bottom electrode in the contact holes; and

forming a variable resistance pattern on the lower insulating pattern electrically connected to the bottom electrode.

11. The method of claim 10, further comprising forming a vertical cell diode within the contact hole, wherein the bottom electrode is formed on the vertical cell diode.

12. The method of claim 11, wherein the forming of the bottom electrode includes conformally forming a conductive layer on the vertical cell diode and along sidewalls of the contact hole, forming a first internal insulating layer on the conductive layer to fill up the contact hole, and removing the conductive layer formed along portions of the sidewalls of the contact hole to form the bottom electrode.

13. The method of claim 12, further comprising forming a second internal insulating layer on the bottom electrode to fill the contact hole.

14. The method of claim 12, wherein the contact hole has a quadrilateral shape including opposite first and second sidewalls and opposite third and fourth sidewalls adjacent to the first sidewall, and, in the removing of the conductive layer formed along portions of the sidewalls of the contact hole, the conductive layer formed along the first sidewall and portions of the third and fourth sidewalls are etched from a top surface of the contact hole.

15. The method of claim 11, wherein the bottom electrode includes a base and a sidewall formed along edges of the base, and

further comprising forming an internal insulating layer on the bottom electrode to fill the contact hole and forming an upper insulating pattern on the lower insulating pattern to cover a portion of a top surface of the sidewall.

16. The method of claim 10, further comprising forming bit lines extending in the second direction on the variable resistance pattern, wherein the contact hole has a width extending along the first direction and a length extending along the second direction and the width is greater than the length.

17. The method of claim 16, wherein the variable resistance pattern extends along the second direction and the variable resistance pattern has a width less than the width of the contact hole.

18. The method of claim 10, wherein the variable resistance pattern includes a phase change material.