Methods for a multiple die integrated circuit package

• US 8,030,135 B2
• Filed: 04/27/2009
• Issued: 10/04/2011
• Est. Priority Date: 11/01/2005
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Wallace, Robert F.
• Primary Examiner(s): WILCZEWSKI, MARY A
• Application Number:
  US12/430,388
• Publication Number:
  US 20090239340A1
• Time in Patent Office: 890 Days
• Field of Search: 438/109, 438/123, 257/E21.499
• US Class Current: 438/109
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/32014 the layer connector being smaller than the bonding area, e.g. bond pad
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 23/4951 Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
• CPC Class Codes: H01L 23/49537 Plurality of lead frames mounted in one device
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

Methods for a multiple die package for integrated circuits are disclosed. An insulator layer is provided and one or more vias are formed within it. The insulator may be provided without vias, and vias formed later. At least one integrated circuit is provided and electrically coupled to at least one lead of a first leadframe overlying one surface of the insulator. At least one second integrated circuit is provided and electrically coupled to a second leadframe overlying a second surface of the insulator. Electrical connections between the two leadframes and the first and second integrated circuits are made through the insulator at selected locations, by coupling at least one lead of the first and second leadframes one to another. The leads of the first and second leadframe may be physically coupled by a welding process within vias in the insulator. A method for a removable storage card is also described.

Claims

1. A method for forming a multiple integrated circuit package, comprising the steps of:

providing an insulator that is selectively anisotropically conductive having a first surface and a second opposing surface;

providing a first leadframe having a plurality of leads partially overlying said first surface;

providing at least one first integrated circuit adjacent to and electrically coupled to at least one of the leads of said first leadframe;

providing at least one second integrated circuit adjacent to and electrically coupled to at least one of the leads of a second leadframe partially overlying said second surface; and

forming an electrical connection between at least one lead of said first leadframe and at least one corresponding lead of said second leadframe by selectively causing the anisotropically conductive insulator to become electrically conductive at selected locations;

whereby the first and second integrated circuits are electrically coupled one to another.

2. The method of claim 1, and further comprising encapsulating the insulator, the first and second integrated circuit dies, and portions of the first and second leadframes to form a sealed package.

3. The method of claim 1, wherein the steps of providing at least one first integrated circuit and at least one second integrated circuit comprise providing identical memory array circuits.

4. The method of claim 1, wherein the steps of providing at least one first integrated circuit and at least one second integrated circuit comprise providing a memory array circuit and a controller circuit for controlling the memory array circuit.

5. A method of claim 1, said second leadframe having at least some leads with a downset portion forming an area for making external connections.

6. The method of claim 1, wherein the step of selectively causing the anisotropically conductive insulator to become electrically conductive at selected locations comprises the step of selectively causing the anisotropically conductive insulator to become electrically conductive at selected locations by applying pressure to the selected locations.

7. The method of claim 1, wherein the step of selectively causing the anisotropically conductive insulator to become electrically conductive at selected locations comprises the step of selectively causing the anisotropically conductive insulator to become electrically conductive at selected locations by applying heat to the selected locations.

8. A method for forming a multiple integrated circuit package, comprising the steps of:

providing an insulator that is anisotropically conductive in portions, the insulator having a first surface and a second opposing surface;

providing a first leadframe having a plurality of leads partially overlying said first surface;

providing at least one first integrated circuit adjacent to and electrically coupled to at least one of the leads of said first leadframe;

providing at least one second integrated circuit adjacent to and electrically coupled to at least one of the leads of a second leadframe partially overlying said second surface;

applying pressure at least to the anisotropically conductive portions of the insulator, the pressure causing the anisotropically conductive portions of the insulator to become conductive;

forming an electrical connection between at least one lead of said first leadframe and at least one corresponding lead of said second leadframe upon the anisotropically conductive insulator becoming conductive at the anisotropically conductive portions of the insulator;

whereby the first and second integrated circuits are electrically coupled one to another.

9. The method of claim 8, and further comprising encapsulating the insulator, the first and second integrated circuit dies, and portions of the first and second leadframes to form a sealed package.

10. The method of claim 8, wherein the steps of providing at least one first integrated circuit and at least one second integrated circuit comprise providing identical memory array circuits.

11. The method of claim 8, wherein the steps of providing at least one first integrated circuit and at least one second integrated circuit comprise providing a memory array circuit and a controller circuit for controlling the memory array circuit.

12. A method for forming a multiple integrated circuit package, comprising the steps of:

providing an insulator that is anisotropically conductive in portions, the insulator having a first surface and a second opposing surface;

providing a first leadframe having a plurality of leads partially overlying said first surface;

providing at least one first integrated circuit adjacent to and electrically coupled to at least one of the leads of said first leadframe;

providing at least one second integrated circuit adjacent to and electrically coupled to at least one of the leads of a second leadframe partially overlying said second surface;

applying heat at least to the anisotropically conductive portions of the insulator, the heat causing the anisotropically conductive portions of the insulator to become conductive;

forming an electrical connection between at least one lead of said first leadframe and at least one corresponding lead of said second leadframe upon the anisotropically conductive insulator becoming conductive at the anisotropically conductive portions of the insulator;

whereby the first and second integrated circuits are electrically coupled one to another.

13. The method of claim 12, and further comprising encapsulating the insulator, the first and second integrated circuit dies, and portions of the first and second leadframes to form a sealed package.

14. The method of claim 12, wherein the steps of providing at least one first integrated circuit and at least one second integrated circuit comprise providing identical memory array circuits.

15. The method of claim 12, wherein the steps of providing at least one first integrated circuit and at least one second integrated circuit comprise providing a memory array circuit and a controller circuit for controlling the memory array circuit.