Method of fabricating trench-constrained isolation diffusion for semiconductor devices

• US 8,030,152 B2
• Filed: 07/31/2008
• Issued: 10/04/2011
• Est. Priority Date: 08/14/2002
• Status: Expired due to Fees

• Current Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Original Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Inventors: Cornell, Michael E., Williams, Richard K., Chan, Wai Tien
• Primary Examiner(s): HA, NATHAN W
• Application Number:
  US12/221,155
• Publication Number:
  US 20080293214A1
• Time in Patent Office: 1,160 Days
• Field of Search: 438/433, 438/207, 257/509, 257/330, 257/E29.262, 257/E25.055
• US Class Current: 438/207
• CPC Class Codes: H01L 21/8224 comprising a combination of vertical and lateral transistors
• CPC Class Codes: H01L 21/82285 Complementary vertical transistors
• CPC Class Codes: H01L 27/0821 Combination of lateral and vertical transistors only
• CPC Class Codes: H01L 27/0826 Combination of vertical complementary transistors
• CPC Class Codes: H01L 29/6625 Lateral transistors H01L29/66242 and H01L29/66265 take precedence
• CPC Class Codes: H01L 29/66272 Silicon vertical transistors H01L29/66242, H01L29/66257 and H01L29/66265 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor substrate includes a pair of trenches filled with a dielectric material. Dopant introduced into the mesa between the trenches is limited from diffusing laterally when the substrate is subjected to thermal processing. Therefore, semiconductor devices can be spaced more closely together on the substrate, and the packing density of the devices can be increased. Also trench constrained doped region diffuse faster and deeper than unconstrained diffusions, thereby reducing the time and temperature needed to complete a desired depth diffusion. The technique may be used for semiconductor devices such as bipolar transistors as well as isolation regions that electrically isolate the devices from each other. In one group of embodiments, a buried layer is formed at an interface between an epitaxial layer and a substrate, at a location generally below the dopant in the mesa. When the substrate is subjected to thermal processing, the buried layer diffuses upward, the dopant in the mesa diffuses downward until the two dopants merge to form an isolation region or a sinker extending downward from the surface of the epitaxial layer to the buried layer. In another embodiment, dopant is implanted between dielectrically filled trenches at a high energy up to several MeV, then diffused, combining the benefits of deep implantation and trenched constrained diffusion to achive deep diffusions with a minimal thermal budget.

Claims

1. A method of fabricating an isolation diffusion for semiconductor devices comprising:

providing a semiconductor substrate;

forming a pair of trenches in said substrate, the trenches defining a mesa;

substantially filling said trenches with a dielectric material;

after forming and substantially filling said trenches, introducing a dopant into the mesa, the dopant having a junction depth less than a depth of the trenches and extending across the mesa so as to abut a portion of a sidewall of each of said trenches; and

after introducing said dopant into said mesa, heating the substrate so as to cause the dopant to diffuse downward in said substrate and thereby form said isolation diffusion, the dielectric material in the trenches impeding the lateral diffusion of the dopant during said heating.

2. The method of claim 1 wherein after said heating a junction depth of said isolation diffusion is less than said depth of said trenches.

3. The method of claim 1 wherein introducing a dopant comprises introducing a dopant having a conductivity type that is opposite to a conductivity type of the substrate.

4. The method of claim 1 wherein introducing a dopant comprises introducing a dopant having a conductivity type that is the same as a conductivity type of the substrate.

5. The method of claim 1 wherein introducing a dopant comprises implanting a dopant.

6. The method of claim 5 wherein after said heating a junction depth of said isolation diffusion is greater than said depth of said trenches.

7. The method of claim 6 wherein a depth of the trenches is equal to 15% to 20% of a depth of the isolation diffusion after said heating.

8. The method of claim 6 wherein implanting the dopant comprises implanting the dopant at a dose in the range 5E12 cm⁻

2 to 5E15 cm<sup>−

2</sup> and at an energy of less than 140 keV.

9. The method of claim 8 wherein implanting the dopant comprises implanting the dopant at a dose in the range 2E13 cm⁻

2 to 2E14 cm<sup>−

2</sup>.

10. The method of claim 6 wherein a depth of the isolation diffusion after said implanting and prior to said heating is less than 0.5 μ

m.

11. The method of claim 1 wherein introducing a dopant comprises predeposition.

12. The method of claim 10 wherein the depth of said trenches is between 1.2 μ

m and 2.8 μ

m.