Reducing external resistance of a multi-gate device using spacer processing techniques

• US 8,030,163 B2
• Filed: 12/26/2007
• Issued: 10/04/2011
• Est. Priority Date: 12/26/2007
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Shah, Uday, Kavalieros, Jack T., Doyle, Brian S., Pillarisetty, Ravi
• Primary Examiner(s): Landau; Matthew
• Assistant Examiner(s): Hall; Jessica
• Application Number:
  US11/964,593
• Publication Number:
  US 20090166741A1
• Time in Patent Office: 1,378 Days
• Field of Search: 438/157, 438/183, 438/283, 438/300, 257/E21.421, 257/E21.455, 257/E21.623, 257/E21.637
• US Class Current: 438/283
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method includes depositing a sacrificial gate electrode to one or more multi-gate fins. The sacrificial gate electrode is patterned such that it is coupled to a gate region and substantially no sacrificial gate electrode is coupled to source and drain regions. A dielectric film is formed that is coupled to the source and drain regions. The sacrificial gate electrode is removed and a spacer gate dielectric is deposited to the gate region wherein substantially no spacer gate dielectric is deposited to the source and drain regions. The spacer gate dielectric is etched to completely remove the spacer gate dielectric from the gate region area that is to be coupled with a final gate electrode except a remaining pre-determined thickness of spacer gate dielectric that is to be coupled with the final gate electrode that remains coupled with the dielectric film.

Claims

1. A method, comprising:

depositing a sacrificial gate electrode directly on one or more fin structures, the one or more fin structures comprising a top surface, a first sidewall surface and a second sidewall surface, the sacrificial gate electrode directly coupling to the top surface, first sidewall surface and second sidewall surface of the one or more fin structures, the one or more fin structures further comprising portions that will become a gate region, a source region, and a drain region when the one or more fin structures are formed into one or more multi-gate fins, the gate region being disposed between the source and drain regions;

patterning the sacrificial gate electrode such that the sacrificial gate electrode material is coupled to the top surface, first sidewall surface and second sidewall surface in the gate region of the one or more fin structures and substantially no sacrificial gate electrode is coupled to the top surface, first sidewall surface and second sidewall surface in the source and drain regions of the one or more fin structures;

forming a dielectric film coupled to the source and drain regions of the one or more fin structures;

removing the sacrificial gate electrode from the gate region of the one or more fin structures;

depositing spacer gate dielectric to the gate region of the one or more fin structures wherein substantially no spacer gate dielectric is deposited to the source and drain regions of the one or more fin structures, the source and drain regions being protected by the dielectric film; and

etching the spacer gate dielectric to completely, or nearly completely, remove the spacer gate dielectric from the gate region area to be coupled with a final gate electrode except a remaining pre-determined thickness of spacer gate dielectric to be coupled with the final gate electrode that remains coupled with the dielectric film.

2. A method according to claim 1, wherein patterning the sacrificial gate electrode results in a thickness, g, of the sacrificial gate electrode in the direction of the one or more fin structures that is equal to or about equal to the following, where f is a pre-determined final gate electrode critical dimension (CD) and where s is the pre-determined spacer gate dielectric thickness:

g=f+2s.

3. A method according to claim 1, wherein a height of the sacrificial gate electrode is selected such that a height of the remaining spacer gate dielectric after etching the spacer gate dielectric is equal to or about equal to a pre-determined height of the final gate electrode, wherein etching the spacer gate dielectric reduces the height of the remaining spacer gate dielectric.

4. A method according to claim 1, wherein forming a dielectric film comprises:

depositing an oxide material to the sacrificial gate electrode and the source and drain regions of the one or more fin structures; and

polishing the oxide material back to the level of the sacrificial gate electrode.

5. A method according to claim 1, wherein depositing spacer gate dielectric to the gate region of the one or more fin structures comprises conformally growing a nitride material onto the deposited dielectric film while not conformally growing spacer gate dielectric onto the sacrificial gate electrode material and not conformally growing spacer gate dielectric onto the final gate electrode material.

6. A method according to claim 1, wherein substantially no spacer gate dielectric is deposited to the source and drain regions of the one or more fin structures at any time during a gate formation process.

7. A method according to claim 1, wherein the one or more fin structures comprise at least one tri-gate fin, the tri-gate fin having the top surface, the first sidewall surface, and the second sidewall surface wherein etching the spacer gate dielectric substantially removes the spacer gate dielectric from the top surface, the first sidewall surface, and the second sidewall surface of the gate region area to be coupled with the final gate electrode.

8. A method according to claim 1, further comprising:

performing tip implantation prior to forming a dielectric film;

depositing the final gate electrode to the gate region of the one or more fin structures such that the final gate electrode is coupled to the pre-determined thickness of spacer gate dielectric that remains after etching the spacer gate dielectric; and

removing the dielectric film such that the pre-determined thickness of spacer gate dielectric remains coupled to the deposited final gate electrode.

9. A method according to claim 8, wherein patterning the sacrificial gate electrode results in a thickness, g, of the sacrificial gate electrode in the direction of the one or more multi-gate fins that is equal to or about equal to the following, where f is a pre-determined final gate electrode critical dimension (CD) and where s is the pre-determined spacer gate dielectric thickness:

g=f+2s.

10. A method according to claim 9, wherein a height of the sacrificial gate electrode is selected such that a height of the remaining spacer gate dielectric after etching the spacer gate dielectric is equal to or about equal to a pre-determined height of the final gate electrode, wherein etching the spacer gate dielectric reduces the height of the remaining spacer gate dielectric.

11. A method according to claim 10, wherein forming a dielectric film comprises:

depositing an oxide material to the sacrificial gate electrode and the source and drain regions of the one or more fin structures; and

polishing the oxide material back to the level of the sacrificial gate electrode.

12. A method according to claim 11, wherein depositing spacer gate dielectric to the gate region of the one or more fin structures comprises conformally growing a nitride material onto the deposited dielectric film while not conformally growing spacer gate dielectric onto the sacrificial gate electrode material and not conformally growing spacer gate dielectric onto the final gate electrode material.

13. A method according to claim 12, wherein substantially no spacer gate dielectric is deposited to the source and drain regions of the one or more fin structures at any time during a gate formation process.

14. A method according to claim 13, further comprising forming the one or more fin structures before depositing the sacrificial gate electrode to one or more fin structures.

15. A method according to claim 1, wherein the one or more fin structures each have the top surface, the first sidewall surface, and the second sidewall surface, the method further comprising:

epitaxially depositing a semiconductor material to the top surface, the first sidewall surface, and the second sidewall surface of the source and drain regions of the one or more fin structures reduce external resistance (R_ext) in a multi-gate transistor device.

16. A method according to claim 1, further comprising forming the one or more fin structures before depositing the sacrificial gate electrode to one or more fin structures.