Contact barrier structure and manufacturing methods

• US 8,030,210 B2
• Filed: 03/11/2010
• Issued: 10/04/2011
• Est. Priority Date: 05/25/2007
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ke, Chung-Hu, Lee, Wen-Chin, Wang, Ching-Ya
• Primary Examiner(s): Ngo; Ngan
• Assistant Examiner(s): LIU, BENJAMIN T
• Application Number:
  US12/722,247
• Publication Number:
  US 20100167485A1
• Time in Patent Office: 572 Days
• Field of Search: 257/382, 257/E21.593, 257/E21.619, 438/299, 438/655, 438/649, 438/630, 438/721, 438/755
• US Class Current: 438/649
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/76844 Bottomless liners
• CPC Class Codes: H01L 21/7685 the layer covering a conductive structure H01L21/76849 takes precedence
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66515 using self aligned selective metal deposition simultaneously on the gate and on source or drain
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a source/drain region adjacent the gate dielectric; a silicide region on the source/drain region; a metal layer on top of, and physical contacting, the silicide region; an inter-layer dielectric (ILD) over the metal layer; and a contact opening in the ILD. The metal layer is exposed through the contact opening. The metal layer further extends under the ILD. The semiconductor structure further includes a contact in the contact opening.

Claims

1. A method of forming a semiconductor structure, the method comprising:

forming a silicon-containing component;

forming a metal layer on the silicon-containing component;

reacting the metal layer with the silicon-containing component to form a silicide region, wherein a top portion of the metal layer is not consumed by the step of reacting;

selectively removing a first portion of the top portion of the metal layer, wherein a second portion of the top portion of the metal layer remains after the selective removal;

forming a contact over and electrically connected to the second portion of the top portion of the metal layer; and

forming a contact barrier layer at least encircling the contact.

2. The method of claim 1, wherein the first portion of the top portion of the metal layer is vertically aligned to a first portion of the silicon-containing component, and wherein the second portion of the top portion of the metal layer is vertically aligned to a second portion of the silicon-containing component.

3. The method of claim 1, wherein the step of forming the metal layer comprises selectively depositing the metal layer.

4. The method of claim 3, wherein the selective depositing comprises depositing using atomic layer deposition.

5. The method of claim 3, wherein the selective depositing comprises electroless plating.

6. The method of claim 1 further comprising:

forming an inter-layer dielectric (ILD) over the silicon-containing component;

forming an opening in the ILD; and

before the step of forming the contact in the opening, forming the contact barrier layer in the opening.

7. The method of claim 6, wherein the contact barrier layer partially covers a bottom of the opening.

8. The method of claim 6, wherein the contact comprises copper.

9. A method of forming a semiconductor structure, the method comprising:

providing a semiconductor substrate;

forming a gate dielectric over the semiconductor substrate;

forming a gate electrode over the gate dielectric;

forming a source/drain region adjacent the gate dielectric;

forming a metal layer covering at least the source/drain region;

selectively removing a first portion of the metal layer directly over the source/drain region, wherein a second portion of the metal layer directly over the source/drain region is not removed;

after the step of selectively removing the first portion of the metal layer, reacting a bottom portion of the metal layer with the source/drain region to form a silicide region, wherein a top portion of the metal layer remains after the step of reacting;

forming an inter-layer dielectric (ILD) over the silicide region and the gate electrode;

forming a contact in the ILD, wherein the contact is fully situated over, and electrically and directly connected to, the top portion of the metal layer.

10. The method of claim 9, wherein the step of forming the metal layer comprises selective deposition.

11. The method of claim 10, wherein the selective deposition comprises atomic layer deposition.

12. The method of claim 10, wherein the selective deposition comprises electroless plating.

13. The method of claim 9, wherein the step of forming the contact further comprises forming an opening in the ILD, and wherein the method further comprises forming a contact barrier layer in the opening before the step of forming the contact.

14. The method of claim 13, wherein the contact barrier layer only partially covers a bottom of the opening.