Field-effect transistor and method for manufacturing a field-effect transistor

• US 8,030,703 B2
• Filed: 12/26/2007
• Issued: 10/04/2011
• Est. Priority Date: 12/29/2006
• Status: Expired due to Fees

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Kotz, Dietmar, Zelsacher, Rudolf, Poelzl, Martin
• Primary Examiner(s): Parker; Ken A
• Assistant Examiner(s): Diaz; Jose R
• Application Number:
  US11/964,202
• Publication Number:
  US 20080211019A1
• Time in Patent Office: 1,378 Days
• Field of Search: 257/331, 257/E21.428
• US Class Current: 257/331
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A field-effect transistor and a method for manufacturing a field-effect transistor is disclosed. One embodiment includes a substrate having a surface along which a trench is implemented, wherein the trench has a trench bottom and a trench edge. A source area is implemented at the trench edge and a gate electrode at least partially implemented in the trench and separated from the substrate by an insulation layer. The field-effect transistor includes a drain electrode at a side of the substrate facing away from the surface. An additional electrode is implemented between the gate electrode and the trench bottom and electrically insulated from the substrate and an electrical connection between the additional electrode and the gate electrode, wherein the electrical connection has a predetermined ohmic resistance value.

Claims

1. A semiconductor component, comprising:

a substrate having a surface;

a trench formed in the surface and having a trench bottom and a trench edge;

a source area implemented at the trench edge;

a gate electrode at least partially implemented in the trench and separated from the substrate by an insulation layer;

a gate contact contacting the gate electrode;

a drain electrode at a side of the substrate;

an additional electrode implemented between the gate electrode and the trench bottom and electrically insulated from the substrate; and

an electrical connection with a predetermined ohmic resistance value coupled between the additional electrode and the gate electrode,

wherein the predetermined ohmic resistance value is selected so that an equalization of potential between the gate electrode and the additional electrode takes place after a time delay, and

wherein the gate contact and the electrical connection are provided on opposite sides of the trench.

2. The semiconductor of claim 1, wherein the electrical connection comprises a doped polycrystalline material and the semiconductor component is a field-effect transistor.

3. A field-effect transistor, comprising:

a substrate comprising a surface along which a trench is formed, wherein the trench comprises a trench bottom and a trench edge;

a source area implemented at the trench edge;

a gate electrode at least partially implemented in the trench and separated from the substrate by an insulation layer;

a gate contact contacting the gate electrode;

a drain electrode at a side of the substrate facing away from the surface;

an additional electrode which is implemented between the gate electrode and the trench bottom and is electrically insulated from the substrate; and

an electrical connection between the additional electrode and the gate electrode,

wherein the electrical connection comprises a predetermined ohmic resistance value, and

wherein the predetermined ohmic resistance value is selected so that an equalization of potential between the gate electrode and the additional electrode takes place after a time delay, and

wherein the gate contact and the electrical connection are provided on opposite sides of the trench.

4. The field-effect transistor of claim 3, wherein the electrical connection comprises a doped polycrystalline material.

5. The field-effect transistor of claim 3, wherein the gate electrode and the additional electrode are led out of the trench and the electrical connection contacts the gate electrode and the additional electrode outside the trench.

6. The field-effect transistor of claim 3, wherein the gate electrode comprises polycrystalline silicon.

7. The field-effect transistor of claim 3, wherein the additional electrode comprises polycrystalline silicon.

8. The field-effect transistor of claim 3, wherein the source area is formed by a doped area of the substrate.

9. The field-effect transistor of claim 3, wherein a substrate area between the trench bottom and the surface forms a channel area of the field-effect transistor.

10. The field-effect transistor of claim 3, wherein the gate electrode and the additional electrode are formed by layers extending along the trench and running across a trench edge area in parallel to the surface and which are electrically separated within the trench by the insulation layer.

11. A semiconductor structure comprising a recess formed in a surface area of a semiconductor substrate, comprising a bottom and an edge, comprising:

a first means to provide a first electrical contact, wherein the first means is implemented at the edge;

a second means to provide an electrical control contact, wherein the second means is at least partially implemented in the trench and separated from the semiconductor substrate by an insulation layer;

a third means which is implemented between the second means and the bottom and electrically insulated from the semiconductor substrate;

a fourth means between the third means and the second means to decrease a switch-on resistance of the field-effect transistor, wherein the fourth means comprises a predetermined ohmic resistance value; and

a fifth means to provide an external contact for the second means and connected to the second means,

wherein the predetermined ohmic resistance value is selected so that an equalization of potential between the gate electrode and the additional electrode takes place after a time delay, and

wherein the fourth means and the fifth means are provided on opposite sides of the trench.

12. The semiconductor structure of claim 11, comprising

a sixth means to provide a second electrical contact, wherein the sixth means is implemented at a side of the semiconductor substrate facing away from the surface area, wherein the third means influences a current flow between the first means and the sixth means.

13. The semiconductor structure of claim 11, wherein the fourth means comprises a doped semiconductor material and the predetermined ohmic resistance value is determined by a selected doping.

14. The semiconductor structure of claim 11, wherein the predetermined ohmic resistance of the fourth means is set by a geometry of the fourth means.

15. A method for manufacturing a field-effect transistor, comprising:

providing a substrate with a surface,

forming a trench along the surface of the substrate, wherein the trench comprises a trench bottom and a trench edge;

forming a source area;

forming a gate electrode which is at least partially implemented within the trench;

forming a gate contact contacting the gate electrode;

forming a drain electrode at a side of the substrate facing away from the surface;

forming an additional electrode between the gate electrode and the trench bottom;

forming an insulation layer between the gate electrode and the substrate between the substrate and the gate electrode and between the substrate and the additional electrode; and

forming an electrical connection between the additional electrode and the gate electrode,

wherein forming an electrical connection between the additional electrode and the gate electrode comprises setting an ohmic resistance value of the electrical connection such that an equalization of potential between the gate electrode and the additional electrode takes place after a time delay, and

wherein the gate contact and the electrical connection are formed on opposite sides of the trench.

16. The method of claim 15, wherein the electrical connection comprises a predetermined ohmic resistance value.

17. The method of claim 15, wherein forming an electrical connection includes leading out the gate electrode and the additional electrode of the trench and further forming an ohmic contact outside the trench.

18. The method of claim 15, wherein forming the gate electrode or forming the additional electrode includes using a polycrystalline semiconductor material.

19. The method of claim 15, wherein the additional electrode comprises a semiconductor material and the predetermined ohmic resistance is set by a doping of the semiconductor material.

20. The method of claim 15, further comprising forming a channel area in an area of the substrate between the trench bottom and the surface.