Semiconductor device packages with electromagnetic interference shielding

• US 8,030,750 B2
• Filed: 11/19/2009
• Issued: 10/04/2011
• Est. Priority Date: 11/19/2009
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Lee, Yuyong, Kim, Seokbong, Yun, Yeonsun
• Primary Examiner(s): Ha; Nathan W
• Application Number:
  US12/622,415
• Publication Number:
  US 20110115066A1
• Time in Patent Office: 684 Days
• Field of Search: 257678-682, 257/690, 257/E23.141, 438/106
• US Class Current: 257/690
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes a circuit substrate, an electronic device, an encapsulant, and a conductive layer. The substrate includes a carrying surface, an opposing bottom surface, and a pad. The device is disposed adjacent to the carrying surface and is electrically connected to the substrate. The encapsulant is disposed adjacent to the carrying surface, encapsulates the device, and includes a center portion and a surrounding peripheral portion that is less thick than the center portion. An opening exposing the pad is formed in the peripheral portion. The conductive layer conformally covers the encapsulant and traverses the opening to connect to the pad.

Claims

1. A semiconductor device package, comprising:

a circuit substrate including;

a carrying surface;

a bottom surface opposite the carrying surface; and

a pad;

an electronic device disposed adjacent to the carrying surface and electrically connected to the circuit substrate;

an encapsulant disposed adjacent to the carrying surface and encapsulating the electronic device, the encapsulant comprising a center portion and a peripheral portion surrounding the center portion, wherein;

a thickness of the peripheral portion is less than a thickness of the center portion;

an opening exposing the pad of the circuit substrate is formed in the peripheral portion;

a conductive layer conformally covering the encapsulant and traversing the opening to connect to the pad of the circuit; and

a filler disposed in the opening.

2. The semiconductor device package of claim 1, wherein:

the circuit substrate includes a lateral surface extending between the carrying surface and the bottom surface;

the peripheral portion of the encapsulant includes a lateral surface; and

the lateral surface of the peripheral portion is substantially coplanar with the lateral surface of the circuit substrate.

3. The semiconductor device package of claim 1, wherein the thickness of the peripheral portion is substantially uniform.

4. The semiconductor device package of claim 1, wherein the opening exposes a top surface of the pad, and the conductive layer covers a sidewall of the opening and the top surface of the pad.

5. The semiconductor device package of claim 4, wherein the pad is disposed adjacent to the carrying surface of the circuit substrate.

6. The semiconductor device package of claim 1, wherein:

the pad is disposed within the circuit substrate;

the opening penetrates both the peripheral portion of the encapsulant and the circuit substrate; and

the conductive layer covers a sidewall of the opening and connects to the pad, the pad being exposed at the sidewall.

7. The semiconductor device package of claim 6, wherein the pad is disposed adjacent to the carrying surface or disposed adjacent to the bottom surface.

8. The semiconductor device package of claim 1, wherein the pad is grounded.

9. The semiconductor device package of claim 1, wherein the opening comprises a circular hole, a linear slot or a ring-shaped trench.

10. A method of forming a semiconductor device package, comprising:

providing a circuit substrate strip including;

a carrying surface;

a bottom surface opposite the carrying surface; and

a circuit substrate;

disposing an electronic device adjacent to the carrying surface, wherein the electronic device is bonded to the circuit substrate;

forming an encapsulant disposed adjacent to the carrying surface and encapsulating the electronic device;

performing a half-cutting of the encapsulant along a border of the circuit substrate to form a peripheral portion of the encapsulant extending along the border of the circuit substrate, wherein a thickness of the peripheral portion is less than a thickness of a center portion of the encapsulant;

forming an opening in the peripheral portion to expose a pad of the circuit substrate;

forming a conductive layer to conformally cover the encapsulant, wherein the conductive layer is connected to the pad of the circuit substrate through the; and

a filler disposed in the opening.

11. The method of claim 10, wherein the thickness of the peripheral portion is substantially uniform.

12. The method of claim 10, further comprising performing a full-cutting of the peripheral portion of the encapsulant along the border of the circuit substrate to separate the circuit substrate from a remainder of the circuit substrate strip and to separate the peripheral portion from a remainder of the encapsulant.

13. The method of claim 10, wherein forming the opening comprises laser drilling.

14. The method of claim 13, wherein the pad is disposed adjacent to the carrying surface of the circuit substrate strip.

15. The method of claim 13, wherein the conductive layer covers a sidewall of the opening and a top surface of the pad.

16. The method of claim 10, wherein forming the opening comprises mechanical drilling.

17. The method of claim 16, wherein the pad is disposed in an inner layer of the circuit substrate strip, and the opening penetrates both the peripheral portion of the encapsulant and the circuit substrate strip.

18. The method of claim 16, wherein the conductive layer covers a sidewall of the opening and connects to the pad exposed at the sidewall.

19. The method of claim 10, further comprising filling the opening after forming the conductive layer, wherein filling the opening comprises electroplating a metal material or printing a non-conductive material into the opening.