Semiconductor substrates with unitary vias and via terminals, and associated systems and methods

• US 8,030,780 B2
• Filed: 10/16/2008
• Issued: 10/04/2011
• Est. Priority Date: 10/16/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Kirby, Kyle K., Parekh, Kunal R.
• Primary Examiner(s): Chu; Chris
• Application Number:
  US12/253,121
• Publication Number:
  US 20100096759A1
• Time in Patent Office: 1,083 Days
• Field of Search: 257/E21.499, 257/E21.585, 257/E23.068, 257/E25.017, 257/200, 257/621, 257/622, 257/667, 257/680, 257/698, 257/774, 438/107, 438/613, 438/667, 174/255
• US Class Current: 257/774
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/08146 the bonding area connecting to a via connection in the body
• CPC Class Codes: H01L 2224/13006 Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06544 Design considerations for via connections, e.g. geometry or layout
• CPC Class Codes: H01L 2225/06548 Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative method in accordance with a particular embodiment includes forming a blind via in a semiconductor substrate, applying a protective layer to a sidewall surface of the via, and forming a terminal opening by selectively removing substrate material from an end surface of the via, while protecting from removal substrate material against which the protective coating is applied. The method can further include disposing a conductive material in both the via and the terminal opening to form an electrically conductive terminal that is unitary with conductive material in the via. Substrate material adjacent to the terminal can then be removed to expose the terminal, which can then be connected to a conductive structure external to the substrate.

Claims

1. A semiconductor assembly, comprising,

a semiconductor substrate including a substrate material having a first major surface, a second major surface, and an opening extending from the first major surface to the second major surface, the opening including a generally cylindrical portion extending generally normal to the first major surface, the cylindrical portion having a generally smooth, uniform surface, the opening further including a terminal portion extending transverse to the cylindrical portion and intersecting the second major surface, the terminal portion having a width generally parallel to the plane of the first major surface that is greater than a corresponding width of the cylindrical portion;

a single, uniform, homogeneous volume of conductive material disposed in both the cylindrical portion and the terminal portion of the opening, the conductive material forming a conductive path in the cylindrical portion and at least a portion of a conductive terminal in the terminal portion, the conductive terminal having a cross-section that is convexly rounded, wherein the cross-section is taken in a plane normal to the second major surface, wherein the convexly rounded conductive terminal projects away from the second major surface in a direction away from the first major surface, the conductive terminal having a first cross-sectional area and a second cross-sectional area greater than the first cross-sectional area, wherein the first cross-sectional area is in a first plane that is generally parallel to the second major surface and includes an outermost surface of the semiconductor substrate and the second cross-sectional area is in a second plane generally parallel to the first plane and positioned beyond the outermost surface; and

a microelectronic element formed in the substrate material and electrically coupled to the conductive material.

2. The assembly of claim 1:

wherein the conductive terminal includes a solderless material;

wherein an outer boundary of the conductive terminal tapers laterally outwardly in a direction away from the second major surface; and

wherein the assembly further comprises a solder ball attached to the conductive terminal, the solder ball being in contact with the tapered outer boundary of the conductive terminal.

3. The assembly of claim 1 wherein the conductive terminal has an outermost boundary at the terminal portion with a cross-sectional area greater than a cross-sectional area of the opening at the terminal portion.

4. The assembly of claim 1 wherein the conductive material is a solderless material.

5. The assembly of claim 1 wherein the cylindrical portion does not have a scalloped internal surface.

6. The assembly of claim 1 wherein the conductive material is at least 90% copper.

7. The assembly of claim 1 wherein an outer boundary of the conductive terminal projects laterally outwardly in a direction away from the outermost surface of the semiconductor substrate.

8. The assembly of claim 1 wherein the conductive material has a concave, cup-shaped void.

9. The assembly of claim 1 wherein the substrate material forms a portion of a first semiconductor die, and wherein the conductive material is at least 90% copper and wherein the semiconductor assembly further comprises a second semiconductor die having a conductive terminal electrically connected to the conductive terminal of the first semiconductor die.

10. The assembly of claim 1 wherein the conductive terminal has a generally spherical shape intersecting the second major surface of the substrate material and beyond the outermost surface of the semiconductor substrate.

11. The assembly of claim 1 wherein the terminal portion has generally flat walls aligned with crystal planes of the semiconductor substrate material.

12. The assembly of claim 1, further comprising:

a seed layer on an outer boundary of the conductive material at the terminal portion; and

a barrier layer on an outer boundary of the seed layer at the terminal portion, wherein the seed layer and the barrier layer project outward beyond the outermost surface of the semiconductor substrate, and wherein the conductive terminal comprises the seed layer, the barrier layer, and the conductive material.

13. A semiconductor assembly, comprising,

a semiconductor substrate including a substrate material having a first major surface, a second major surface, and an opening extending from the first major surface to the second major surface, the opening including a generally cylindrical portion extending generally normal to the first major surface, the cylindrical portion having a generally smooth, uniform surface, the opening further including a terminal portion extending transverse to the cylindrical portion and intersecting the second major surface, the terminal portion having a width generally parallel to the plane of the first major surface that is greater than a corresponding width of the cylindrical portion;

a single, uniform, homogeneous volume of conductive material disposed in both the cylindrical portion and the terminal portion of the opening, the conductive material forming a conductive path in the cylindrical portion and at least a portion of a conductive terminal at the terminal portion, wherein the conductive terminal has an outermost boundary that projects laterally outward beyond an outermost surface of the semiconductor substrate substantially parallel to the second major surface;

a microelectronic element formed in the substrate material and electrically coupled to the conductive material;

a seed layer on an outer boundary of the conductive material at the terminal portion; and

a barrier layer on an outer boundary of the seed layer at the terminal portion, wherein the seed layer and the barrier layer project outward beyond the outermost surface of the semiconductor substrate, and wherein the conductive terminal comprises the seed layer, the barrier layer, and the conductive material.