Semiconductor integrated circuit

• US 8,030,961 B2
• Filed: 09/03/2010
• Issued: 10/04/2011
• Est. Priority Date: 06/29/2007
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Matsudera, Katsuki
• Primary Examiner(s): CRAWFORD, JASON
• Application Number:
  US12/875,612
• Publication Number:
  US 20100327904A1
• Time in Patent Office: 396 Days
• Field of Search: 326/30, 326 82- 83, 326/86, 326/112, 326/115, 327108-109
• US Class Current: 326/30
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2200/222 A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2203/45691 the LC comprising one or more transistors as active loading resistors
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03K 19/0005 Modifications of input or output impedance

Abstract

A semiconductor integrated circuit includes a control signal generating circuit which is configured to set, at least at a time of a first state, first and fifth control signals at a first voltage level, and second, third and fourth control signals at a second voltage level, and to set, at a time of a second state, the first to fourth control signals at the first voltage level, and the fifth control signal at an arbitrary voltage level.

Claims

1. A semiconductor integrated circuit comprising:

a first variable terminating resistor including a plurality of first transistors of a first conductivity type each having a current path with one end connected to a first power supply and having a control terminal to which one of a plurality of first control signals are input, and a plurality of first resistor elements each having one end connected to the other end of the current path of the associated one of the plurality of first transistors and having the other end connected to a first output terminal;

a second variable terminating resistor including a plurality of second transistors of the first conductivity type each having a current path with one end connected to the first power supply and having a control terminal to which one of a plurality of second control signals are input, and a plurality of second resistor elements each having one end connected to the other end of the current path of the associated one of the plurality of second transistors and having the other end connected to a second output terminal;

a third transistor of a second conductivity type, which has a current path with one end connected to the other end of the first resistor terminal, and has a control terminal to which a third control signal is input;

a fourth transistor of the second conductivity type, which has a current path with one end connected to the other end of the second resistor terminal, and has a control terminal to which a fourth control signal is input;

a fifth transistor of the second conductivity type, which has a current path with one end connected to the other end of the current path of the third transistor and to the other end of the current path of the fourth transistor, and with the other end connected to a second power supply, and has a control terminal to which a fifth control signal is input;

an information holding circuit is configured to generate select signals selecting the first and second control signals; and

a control signal generating circuit which sets, at least at a time of a first state, the plurality of first control signals selected by the information holding circuit, and fifth control signals at a first voltage level, and the second, third and fourth control signals at a second voltage level, and sets, at a time of a second state, the first and second control signals selected by the information holding circuit and the third to fourth control signals at the first voltage level, and the fifth control signal at an arbitrary voltage level.

2. The semiconductor integrated circuit according to claim 1, wherein the control signal generating circuit comprises:

a first NAND circuit having a first input to which a first select signal is input, and having a second input to which a second select signal is input;

a second NAND circuit having a first input to which a third select signal is input, and having a second input to which the second select signal is input; and

a signal generating circuit which generates the first and third select signals.

3. The semiconductor integrated circuit according to claim 1, further comprising:

a first pad which is connected to said one end of the current path of the plurality of first transistors and to said one end of the current path of the plurality of second transistors;

a second pad which is connected to a first output pin via the current path of the third transistor; and

a third pad which is connected to a second output pin via the current path of the fourth transistor.

4. The semiconductor integrated circuit according to claim 1, further comprising:

a bias circuit which outputs a bias signal to the control terminal of the fifth transistor and the control signal generating circuit.

5. The semiconductor integrated circuit according to claim 1, further comprising:

a receiver which functions, together with the semiconductor integrated circuit, as an input/output circuit.

6. The semiconductor integrated circuit according to claim 1, further comprising:

a controller which controls the semiconductor integrated circuit.

7. The semiconductor integrated circuit according to claim 6, further comprising:

a graphic core which includes a plurality or micro-lenses which are arranged in a matrix, and is controlled by the controller; and

a CMOS I/O which receives a graphic signal from the graphic core.