Semiconductor memory device with three-dimensional array and repair method thereof
First Claim
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1. A nonvolatile memory device, comprising:
- a three-dimensional (3D) cell array comprising a plurality of cell arrays located in a corresponding plurality of stacked substrate layers, the cell arrays sharing a bit line;
a column selection circuit selecting a memory unit included in the 3D cell array; and
a fuse block controlling the column selection circuit to repair a plurality of defective columns with one of a plurality of redundant bit lines located in the 3D cell array.
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Abstract
A nonvolatile memory device includes a three-dimensional (3D) cell array, a column selection circuit and a fuse block. The 3D cell array includes multiple cell arrays located in corresponding stacked substrate layers, the cell arrays sharing a bit line. The column selection circuit selects a memory unit included in the 3D cell array. The fuse block controls the column selection circuit to repair defective columns with one of multiple redundant bit lines located in the 3D cell array.
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Citations
25 Claims
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1. A nonvolatile memory device, comprising:
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a three-dimensional (3D) cell array comprising a plurality of cell arrays located in a corresponding plurality of stacked substrate layers, the cell arrays sharing a bit line; a column selection circuit selecting a memory unit included in the 3D cell array; and a fuse block controlling the column selection circuit to repair a plurality of defective columns with one of a plurality of redundant bit lines located in the 3D cell array. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 25)
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9. A nonvolatile memory device, comprising:
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a three-dimensional (3D) cell array comprising a plurality of cell arrays formed in a corresponding plurality of stacked substrate layers, the cell arrays sharing a bit line; a column selection circuit selecting a bit line connected to the 3D cell array; and a fuse block controlling the column selection circuit to repair a plurality of defective columns using one of redundant bit lines located in the 3D cell array in response to a layer address and a column address corresponding to the substrate layer, wherein the 3D cell array further comprises; first memory units corresponding to the substrate layers and connected to a first bit line; second memory units corresponding to the substrate layers and connected to a second bit line; and redundant memory units corresponding to the substrate layers and connected to a redundant bit line. - View Dependent Claims (10, 11, 12, 13)
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14. A nonvolatile memory device comprising:
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a three-dimensional (3D) cell array comprising a plurality of cell arrays formed in a corresponding plurality of stacked substrate layers, the cell arrays sharing a bit line; a column selection circuit selecting a bit line connected to the 3D cell array; and a fuse block controlling the column selection circuit to repair a defective column with a redundant bit line located in the 3D cell array in response to a column address, wherein the 3D cell array further comprises; a plurality of first memory units corresponding to the plurality of substrate layers and connected to a first bit line; a plurality of second memory units corresponding to the plurality of substrate layers and connected to a second bit line; a plurality of first redundant memory units corresponding to the plurality of substrate layers and connected to a first redundant bit line; and a plurality of second redundant memory units corresponding to the substrate layers and connected to a second redundant bit line. - View Dependent Claims (15, 16, 17)
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18. A nonvolatile memory device comprising:
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a three-dimensional (3D) cell array comprising a plurality of cell arrays located in a plurality of stacked substrate layers; a plurality of row decoders corresponding to the plurality of cell arrays and selecting memory blocks of the plurality of cell arrays; and a fuse block controlling the plurality of row decoders to repair defective memory blocks of cell arrays with redundant memory blocks located in the cell arrays. - View Dependent Claims (19, 20, 21)
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22. A nonvolatile memory device comprising:
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a three-dimensional (3D) cell array comprising a plurality of cell arrays in a corresponding plurality of stacked substrate layers; a plurality of row decoders corresponding to the plurality of substrate layers and selecting memory blocks from the cell arrays; and a fuse block controlling the plurality of row decoders to repair defective memory blocks of the cell arrays with a redundant memory block of the substrate layer having one of the cell arrays. - View Dependent Claims (23, 24)
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Specification