Packet switching

• US 8,031,606 B2
• Filed: 06/24/2008
• Issued: 10/04/2011
• Est. Priority Date: 06/24/2008
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Memon, Mazhar I., King, Steven R.
• Primary Examiner(s): Moe; Aung S
• Assistant Examiner(s): Elliott, IV; Benjamin H
• Application Number:
  US12/145,236
• Publication Number:
  US 20090316711A1
• Time in Patent Office: 1,197 Days
• Field of Search: 370/235, 370/252, 370/352, 370/359, 370/412, 370/419, 710/29, 710/39, 718/100
• US Class Current: 370/235
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/24 Traffic characterised by specific attributes, e.g. priority or QoS
• CPC Class Codes: H04L 47/2433 Allocation of priorities to traffic types
• CPC Class Codes: H04L 47/2475 for supporting traffic characterised by the type of applications
• CPC Class Codes: H04L 47/2483 involving identification of individual flows
• CPC Class Codes: H04L 47/32 by discarding or delaying data units, e.g. packets or frames
• CPC Class Codes: H04L 47/50 Queue scheduling
• CPC Class Codes: H04L 47/6255 queue load conditions, e.g. longest queue first
• CPC Class Codes: H04L 47/627 policing
• CPC Class Codes: H04L 49/109 Integrated on microchip, e.g. switch-on-chip

Abstract

In an embodiment, an apparatus is provided that may include an integrated circuit including switch circuitry to determine, at least in part, an action to be executed involving a packet. This determination may be based, at least in part, upon flow information determined, at least in part, from the packet, and packet processing policy information. The circuitry may examine the policy information to determine whether a previously-established packet processing policy has been established that corresponds, at least in part, to the flow information. If the circuitry determines, at least in part, that the policy has not been established and the packet is a first packet in a flow corresponding at least in part to the flow information, the switch circuitry may request that at least one switch control program module establish, at least in part, a new packet processing policy corresponding, at least in part, to the flow information.

Claims

1. An apparatus comprising:

an integrated circuit including switch circuitry to determine, at least in part, an action to be executed involving a packet, determination of the action being based, at least in part, upon flow information determined, at least in part, from the packet, and packet processing policy information, the switch circuitry being to examine, at least in part, the policy information to determine, at least in part, whether a previously-established packet processing policy has been established that corresponds, at least in part, to the flow information, and if the switch circuitry determines, at least in part, that the policy has not been established and the packet is a first packet in a flow corresponding at least in part to the flow information, the switch circuitry being to request that at least one switch control program module establish, at least in part, a new packet processing policy corresponding, at least in part, to the flow information;

if the switch circuitry determines, at least in part, that the previously-established policy has not been established, the switch circuitry is also to place the packet in a queue and increment a counter indicating, at least in part, a number of packets in the flow that are in the queue;

after the packet has been placed in the queue, the switch circuitry also is to re-examine, at least in part, the policy information to determine, at least in part, whether the new packet processing policy has been established;

after re-examining, at least in part, the policy information, if the switch circuitry determines, at least in part, that the new packet processing policy has been established, the switch circuitry is to remove the packet from the queue and decrement the counter; and

if, after the packet has been placed in the queue, the packet becomes a head of the queue and no action has been indicated, at least in part, in a tuple corresponding at least in part to the flow information, the switch circuitry is to carry out the action after the action has been indicated, at least in part, in the tuple, the tuple to be stored in the integrated circuit, the tuple to store values in mutual association with each other, the values representing at least one packet bit mask, at least one offset in a given packet at which the flow information is expected to be found, the flow information, the action, and the counter.

2. The apparatus of claim 1, wherein:

the processor executes, at least in part, the at least one module;

a host processor comprises the processor;

an integrated circuit chip comprises the integrated circuit; and

the integrated circuit chip also comprises a network interface controller and the host processor.

3. The apparatus of claim 1, wherein:

the processor executes, at least in part, the at least one module;

an integrated circuit chip comprises the processor; and

another integrated circuit chip comprises the integrated circuit.

4. The apparatus of claim 1, wherein:

the policy information indicates, at least in part, the action; and

the action comprises one of placing the packet in a virtual machine queue and dropping the packet.

5. The apparatus of claim 4, wherein:

if the switch circuitry determines, at least in part, that the previously-established policy has been established, the switch circuitry is to carry out, at least in part, the action.

6. The apparatus of claim 1, wherein:

the switch circuitry is to place the packet in a queue if at least one other packet from the flow is also in the queue.

7. A method comprising:

determining, at least in part from a packet, flow information;

determining at least in part by switch circuitry comprised in an integrated circuit an action to be executed involving the packet, the determining, at least in part, of the action being based, at least in part, upon the flow information and packet processing policy information, the packet processing policy information being determined based at least in part upon examining, at least in part, by the switch circuitry of the packet processing policy information to determine whether a previously-established packet processing policy has been established that corresponds, at least in part, to the flow information, and if the switch circuitry determines, at least in part, that the policy has not been established and the packet is a first packet in a flow corresponding at least in part to the flow information, the switch circuitry being to request that at least one switch control program module establish, at least in part, a new packet processing policy corresponding, at least in part, to the flow information;

if the switch circuitry determines, at least in part, that the previously-established policy has not been established, the switch circuitry is also to place the packet in a queue and increment a counter indicating, at least in part, a number of packets in the flow that are in the queue;

after the packet has been placed in the queue, the switch circuitry also is to re-examine, at least in part, the policy information to determine, at least in part, whether the new packet processing policy has been established;

after re-examining, at least in part, the policy information, if the switch circuitry determines, at least in part, that the new packet processing policy has been established, the switch circuitry is to remove the packet from the queue and decrement the counter; and

if, after the packet has been placed in the queue, the packet becomes a head of the queue and no action has been indicated, at least in part, in a tuple corresponding at least in part to the flow information, the switch circuitry is to carry out the action after the action has been indicated, at least in part, in the tuple, the tuple to be stored in the integrated circuit, the tuple to store values in mutual association with each other, the values representing at least one packet bit mask, at least one offset in a given packet at which the flow information is expected to be found, the flow information, the action, and the counter.

8. The method of claim 7, wherein:

the processor executes, at least in part, the at least one module;

a host processor comprises the processor;

an integrated circuit chip comprises the integrated circuit; and

the integrated circuit chip also comprises a network interface controller and the host processor.

9. The method of claim 7, wherein:

the processor executes, at least in part, the at least one module;

an integrated circuit chip comprises the processor; and

another integrated circuit chip comprises the integrated circuit.

10. The method of claim 7, wherein:

the policy information indicates, at least in part, the action; and

the action comprises one of placing the packet in a virtual machine queue and dropping the packet.

11. The method of claim 10, wherein:

if the switch circuitry determines, at least in part, that the previously-established policy has been established, the switch circuitry is to carry out, at least in part, the action.

12. Machine-readable memory storing one or more instructions that when executed by a machine result in execution of operations comprising:

determining, at least in part from a packet, flow information;

determining at least in part by switch circuitry comprised in an integrated circuit an action to be executed involving the packet, the determining, at least in part, of the action being based, at least in part, upon the flow information and packet processing policy information, the packet processing policy information being determined based at least in part upon examining, at least in part, by the switch circuitry of the packet processing policy information to determine whether a previously-established packet processing policy has been established that corresponds, at least in part, to the flow information, and if the switch circuitry determines, at least in part, that the policy has not been established and the packet is a first packet in a flow corresponding at least in part to the flow information, the switch circuitry being to request that at least one switch control program module establish, at least in part, a new packet processing policy corresponding, at least in part, to the flow information;

if the switch circuitry determines, at least in part, that the previously-established policy has not been established, the switch circuitry is also to place the packet in a queue and increment a counter indicating, at least in part, a number of packets in the flow that are in the queue;

after the packet has been placed in the queue, the switch circuitry also is to re-examine, at least in part, the policy information to determine, at least in part, whether the new packet processing policy has been established;

after re-examining, at least in part, the policy information, if the switch circuitry determines, at least in part, that the new packet processing policy has been established, the switch circuitry is to remove the packet from the queue and decrement the counter; and

if, after the packet has been placed in the queue, the packet becomes a head of the queue and no action has been indicated, at least in part, in a tuple corresponding at least in part to the flow information, the switch circuitry is to carry out the action after the action has been indicated, at least in part, in the tuple, the tuple to be stored in the integrated circuit, the tuple to store values in mutual association with each other, the values representing at least one packet bit mask, at least one offset in a given packet at which the flow information is expected to be found, the flow information, the action, and the counter.

13. The memory of claim 12, wherein:

the processor executes, at least in part, the at least one module;

a host processor comprises the processor;

an integrated circuit chip comprises the integrated circuit; and

the integrated circuit chip also comprises a network interface controller and the host processor.

14. The memory of claim 12, wherein:

the processor executes, at least in part, the at least one module;

an integrated circuit chip comprises the processor; and

another integrated circuit chip comprises the integrated circuit.

15. The memory of claim 12, wherein:

the policy information indicates, at least in part, the action; and

the action comprises one of placing the packet in a virtual machine queue and dropping the packet.

16. The memory of claim 15, wherein:

if the switch circuitry determines, at least in part, that the previously-established policy has been established, the switch circuitry is to carry out, at least in part, the action.

17. The memory of claim 12, wherein:

the switch circuitry is to place the packet in a queue if at least one other packet from the flow is also in the queue.