System for receiving transport streams

• US 8,032,910 B2
• Filed: 05/12/2010
• Issued: 10/04/2011
• Est. Priority Date: 04/12/2001
• Status: Active Grant

• Current Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Inventors: Lewis, David, Gurney, Howard
• Primary Examiner(s): Hirl; Joseph P
• Assistant Examiner(s): Peng; Fred
• Application Number:
  US12/778,413
• Publication Number:
  US 20100284408A1
• Time in Patent Office: 510 Days
• Field of Search: None
• US Class Current: 725/68
• CPC Class Codes: H04N 21/42646 for reading from or writing on a non-volatile solid state storage medium, e.g. DVD, CD-ROM
• CPC Class Codes: H04N 21/42661 for reading from or writing on a magnetic storage medium, e.g. hard disk drive
• CPC Class Codes: H04N 21/42669 the medium being removable
• CPC Class Codes: H04N 21/42692 for reading from or writing on a volatile storage medium, e.g. Random Access Memory [RAM]
• CPC Class Codes: H04N 21/434 Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream demultiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00
• CPC Class Codes: H04N 21/4383 Accessing a communication channel
• CPC Class Codes: H04N 21/44004 involving video buffer management, e.g. video decoder buffer or video display buffer

Abstract

A system comprising first input means for receiving a transport stream from an external source, second input means for receiving an input from a memory, means for connecting the first and second input means to an interface which is arranged to provide an output stream to a decoder. The second input means is arranged to provide an output to the interface in such a form that the interface does not distinguish between the output from the first and second input means.

Claims

1. A system comprising:

at least one first input component for receiving a first transport stream from an external source;

at least one second input component for receiving a second transport stream from a memory; and

at least one multiplexer for connecting the at least one first input component and the at least one second input component to an interface which is arranged to provide an output stream to a decoder;

wherein the at least one second input component comprises;

a configuration register comprising a software configuration value used to indicate to the interface that a predetermined amount of data is available to be output from a buffer in a software writable transport stream register, and

the software writable transport stream register comprising a pace counter that controls a stream data rate of transfer of the second transport stream from the memory to the interface so that the transport stream is re-playable via at least fast forward and rewind, wherein;

when the pace counter matches the software configuration value, a valid signal is asserted for one system clock cycle and provided to the interface,

the valid signal indicates that at least one byte read from the buffer is valid, and

the amount of cycles between each valid byte output by the at least one second input component is programmed in the pace counter.

2. The system as claimed in claim 1, wherein said at least one second input component from memory comprises a transport stream.

3. The system as claimed in claim 1, wherein, when a predetermined amount of space in the buffer is available, a software request flag is asserted.

4. The system as claimed in claim 1, wherein said buffer comprises a first-in-first out (FIFO) buffer.

5. The system as claimed in claim 1, wherein half the size of the buffer equals a bit rate of the data input to the at least one second input component multiplied by a time it takes to read the data from the memory and write the data to the at least one second input component.

6. The system as claimed in claim 1, wherein the software writable transport stream register is provided in said at least one second input component to convert a serial stream of data into a parallel stream of data.

7. The system as claimed in claim 1, wherein said memory is external to said system.

8. The system as claimed in claim 1, wherein said memory is in said system.

9. The system as claimed in claim 1, wherein said memory comprises at least one of CD-ROM, hard disk, floppy disk, CPU, and RAM.

10. The system as claimed in claim 1, wherein said at least one first input component is arranged to receive a transport stream from a cable or satellite link.

11. The system as claimed in claim 1, wherein said at least one second input component comprises a clock, said clock providing a clock signal for controlling the output of data to said at least one second input component.

12. The system as claimed in claim 1, wherein said at least one second input component is arranged to output valid data only.

13. The system of claim 1, wherein the at least one second input component provides an output to the interface in such a form that the interface is not able to determine if the output comes from the external source or from the memory.

14. An integrated circuit comprising:

at least one first input component for receiving a first transport stream from an external source;

at least one second input component for receiving a second transport stream from a memory; and

at least one multiplexer for connecting the at least one first input component and the at least one second input component to an interface which is arranged to provide an output stream to a decoder;

wherein the at least one second input component comprises;

a configuration register comprising a software configuration value used to indicate to the interface that a predetermined amount of data is available to be output from a buffer in a software writable transport stream register, and

the software writable transport stream register comprising a pace counter that controls a stream data rate of transfer of the second transport stream from the memory to the interface so that the transport stream is re-playable via at least fast forward and rewind, wherein;

when the pace counter matches the software configuration value, a valid signal is asserted for one system clock cycle and provided to the interface,

the valid signal indicates that at least one byte read from the buffer is valid, and

the amount of cycles between each valid byte output by the at least one second input component is programmed in the pace counter.

15. The integrated circuit of claim 14, wherein the at least one second input component provides an output to the interface in such a form that the interface is not able to determine if the output comes from the external source or from the memory.

16. A set top box comprising:

at least one first input component for receiving a broadcast transport stream from an external source;

at least one second input component for receiving a transport stream from a memory; and

at least one multiplexer for connecting the at least one first input component and the at least one second input component to an interface which is arranged to provide an output stream to a decoder;

wherein at least one the second input component comprises;

a configuration register comprising a software configuration value used to indicate to the interface that a predetermined amount of data is available to be output from a buffer in a software writable transport stream register, and

the software writable transport stream register comprising a pace counter that controls a stream data rate of transfer of the transport stream from the memory to the interface so that the transport stream is re-playable via at least fast forward and rewind, wherein;

when the pace counter matches the software configuration value, a valid signal is asserted for one system clock cycle and provided to the interface,

the valid signal indicates that at least one byte read from the buffer is valid, and

the amount of cycles between each valid byte output by the at least one second input component is programmed in the pace counter.

17. The set top box of claim 16, wherein the at least one second input component provides an output to the interface in such a form that the interface is not able to determine if the output comes from the external source or from the memory.